diff options
| -rw-r--r-- | Makefile | 14 | ||||
| -rw-r--r-- | design/intercon.v | 164 | ||||
| l--------- | tests/intercon/operations0.memv | 1 | ||||
| l--------- | tests/intercon/operations1.memv | 1 | ||||
| -rw-r--r-- | tests/intercon/test.v | 239 | ||||
| -rw-r--r-- | tests/master_arbiter/operations0.memv | 34 | ||||
| -rw-r--r-- | tests/master_arbiter/operations1.memv | 34 |
7 files changed, 452 insertions, 35 deletions
@@ -49,13 +49,14 @@ STACK_MACHINE_TESTS := \ TESTS := \ self \ self_32bit_word \ - slave_dispatcher \ div \ vga \ sram_slave \ embedded_bram_slave \ soc_simple_display \ interface_wrapper \ + intercon \ + slave_dispatcher \ master_arbiter \ $(addprefix stack_machine_old_,$(STACK_MACHINE_OLD_TESTS)) \ $(addprefix stack_machine_,$(STACK_MACHINE_TESTS)) @@ -171,6 +172,17 @@ tests/master_arbiter/test.vvp : tests/master_arbiter/operations0.mem \ $(filter %1.mem,$^)) \ $(filter %.v,$^) -o $@ +tests/intercon/test.vvp : tests/intercon/operations0.mem \ + tests/intercon/operations1.mem tests/intercon/test.v \ + models/slave.v models/master.v design/intercon.v \ + design/slave_dispatcher.v design/master_arbiter.v \ + include/messages.vh + $(IV) $(IVFLAGS) -s intercon_test \ + -DMASTER0_OPERATIONS_COUNT=$(call FILE_LINES,$<) \ + -DMASTER1_OPERATIONS_COUNT=$(call FILE_LINES,\ + $(filter %1.mem,$^)) \ + $(filter %.v,$^) -o $@ + tests/embedded_bram_slave/test.vvp : tests/embedded_bram_slave/operations.mem \ tests/embedded_bram_slave/rom.mem \ tests/embedded_bram_slave/test.v models/master.v \ diff --git a/design/intercon.v b/design/intercon.v new file mode 100644 index 0000000..926414d --- /dev/null +++ b/design/intercon.v @@ -0,0 +1,164 @@ +/* All this module does is combining slave_dispatcher with master_arbiter */ +`default_nettype none + +module intercon + ( + input wire CLK, + input wire RST, + + input wire S0_ACK_O, + output wire [17:0] S0_ADR_I, + output wire [15:0] S0_DAT_I, + input wire [15:0] S0_DAT_O, + output wire S0_STB_I, + output wire S0_WE_I, + input wire S0_STALL_O, + + input wire S1_ACK_O, + output wire [17:0] S1_ADR_I, + output wire [15:0] S1_DAT_I, + input wire [15:0] S1_DAT_O, + output wire S1_STB_I, + output wire S1_WE_I, + input wire S1_STALL_O, + + input wire S2_ACK_O, + output wire [17:0] S2_ADR_I, + output wire [15:0] S2_DAT_I, + input wire [15:0] S2_DAT_O, + output wire S2_STB_I, + output wire S2_WE_I, + input wire S2_STALL_O, + + input wire S3_ACK_O, + output wire [17:0] S3_ADR_I, + output wire [15:0] S3_DAT_I, + input wire [15:0] S3_DAT_O, + output wire S3_STB_I, + output wire S3_WE_I, + input wire S3_STALL_O, + + output wire M0_ACK_I, + input wire [19:0] M0_ADR_O, + output wire [15:0] M0_DAT_I, + input wire [15:0] M0_DAT_O, + input wire M0_STB_O, + input wire M0_CYC_O, + input wire M0_WE_O, + output wire M0_STALL_I, + + output wire M1_ACK_I, + input wire [19:0] M1_ADR_O, + output wire [15:0] M1_DAT_I, + input wire [15:0] M1_DAT_O, + input wire M1_STB_O, + input wire M1_CYC_O, + input wire M1_WE_O, + output wire M1_STALL_I + ); + + wire S_COMBINED_ACK_O; + wire [19:0] S_COMBINED_ADR_I; + wire [15:0] S_COMBINED_DAT_I; + wire [15:0] S_COMBINED_DAT_O; + wire S_COMBINED_STB_I; + wire S_COMBINED_WE_I; + wire S_COMBINED_STALL_O; + + wire M_COMBINED_ACK_I; + wire [19:0] M_COMBINED_ADR_O; + wire [15:0] M_COMBINED_DAT_I; + wire [15:0] M_COMBINED_DAT_O; + wire M_COMBINED_STB_O; + wire M_COMBINED_CYC_O; + wire M_COMBINED_WE_O; + wire M_COMBINED_STALL_I; + + slave_dispatcher dispatcher + ( + .CLK(CLK), + .RST(RST), + + .S0_ACK_O(S0_ACK_O), + .S0_ADR_I(S0_ADR_I), + .S0_DAT_I(S0_DAT_I), + .S0_DAT_O(S0_DAT_O), + .S0_STB_I(S0_STB_I), + .S0_WE_I(S0_WE_I), + .S0_STALL_O(S0_STALL_O), + + .S1_ACK_O(S1_ACK_O), + .S1_ADR_I(S1_ADR_I), + .S1_DAT_I(S1_DAT_I), + .S1_DAT_O(S1_DAT_O), + .S1_STB_I(S1_STB_I), + .S1_WE_I(S1_WE_I), + .S1_STALL_O(S1_STALL_O), + + .S2_ACK_O(S2_ACK_O), + .S2_ADR_I(S2_ADR_I), + .S2_DAT_I(S2_DAT_I), + .S2_DAT_O(S2_DAT_O), + .S2_STB_I(S2_STB_I), + .S2_WE_I(S2_WE_I), + .S2_STALL_O(S2_STALL_O), + + .S3_ACK_O(S3_ACK_O), + .S3_ADR_I(S3_ADR_I), + .S3_DAT_I(S3_DAT_I), + .S3_DAT_O(S3_DAT_O), + .S3_STB_I(S3_STB_I), + .S3_WE_I(S3_WE_I), + .S3_STALL_O(S3_STALL_O), + + .S_COMBINED_ACK_O(S_COMBINED_ACK_O), + .S_COMBINED_ADR_I(S_COMBINED_ADR_I), + .S_COMBINED_DAT_I(S_COMBINED_DAT_I), + .S_COMBINED_DAT_O(S_COMBINED_DAT_O), + .S_COMBINED_STB_I(S_COMBINED_STB_I), + .S_COMBINED_WE_I(S_COMBINED_WE_I), + .S_COMBINED_STALL_O(S_COMBINED_STALL_O) + ); + + master_arbiter arbiter + ( + .CLK(CLK), + .RST(RST), + + .M0_ACK_I(M0_ACK_I), + .M0_ADR_O(M0_ADR_O), + .M0_DAT_I(M0_DAT_I), + .M0_DAT_O(M0_DAT_O), + .M0_STB_O(M0_STB_O), + .M0_CYC_O(M0_CYC_O), + .M0_WE_O(M0_WE_O), + .M0_STALL_I(M0_STALL_I), + + .M1_ACK_I(M1_ACK_I), + .M1_ADR_O(M1_ADR_O), + .M1_DAT_I(M1_DAT_I), + .M1_DAT_O(M1_DAT_O), + .M1_STB_O(M1_STB_O), + .M1_CYC_O(M1_CYC_O), + .M1_WE_O(M1_WE_O), + .M1_STALL_I(M1_STALL_I), + + .M_COMBINED_ACK_I(M_COMBINED_ACK_I), + .M_COMBINED_ADR_O(M_COMBINED_ADR_O), + .M_COMBINED_DAT_I(M_COMBINED_DAT_I), + .M_COMBINED_DAT_O(M_COMBINED_DAT_O), + .M_COMBINED_STB_O(M_COMBINED_STB_O), + .M_COMBINED_CYC_O(M_COMBINED_CYC_O), + .M_COMBINED_WE_O(M_COMBINED_WE_O), + .M_COMBINED_STALL_I(M_COMBINED_STALL_I) + ); + + assign M_COMBINED_ACK_I = S_COMBINED_ACK_O; + assign M_COMBINED_DAT_I = S_COMBINED_DAT_O; + assign M_COMBINED_STALL_I = S_COMBINED_STALL_O; + + assign S_COMBINED_ADR_I = M_COMBINED_ADR_O; + assign S_COMBINED_DAT_I = M_COMBINED_DAT_O; + assign S_COMBINED_STB_I = M_COMBINED_STB_O && M_COMBINED_CYC_O; + assign S_COMBINED_WE_I = M_COMBINED_WE_O; +endmodule // intercon diff --git a/tests/intercon/operations0.memv b/tests/intercon/operations0.memv new file mode 120000 index 0000000..013f024 --- /dev/null +++ b/tests/intercon/operations0.memv @@ -0,0 +1 @@ +../master_arbiter/operations0.memv
\ No newline at end of file diff --git a/tests/intercon/operations1.memv b/tests/intercon/operations1.memv new file mode 120000 index 0000000..13fd017 --- /dev/null +++ b/tests/intercon/operations1.memv @@ -0,0 +1 @@ +../master_arbiter/operations1.memv
\ No newline at end of file diff --git a/tests/intercon/test.v b/tests/intercon/test.v new file mode 100644 index 0000000..313f4c6 --- /dev/null +++ b/tests/intercon/test.v @@ -0,0 +1,239 @@ +`default_nettype none + +`include "messages.vh" + +`ifndef MASTER0_OPERATIONS_COUNT + `error_MASTER0_OPERATIONS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + +`ifndef MASTER1_OPERATIONS_COUNT + `error_MASTER1_OPERATIONS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + +`ifndef SIMULATION + `error_SIMULATION_not_defined +; /* Cause syntax error */ +`endif + +module intercon_test(); + reg CLK; + reg RST; + + wire M0_ACK_I, M1_ACK_I; + wire [19:0] M0_ADR_O, M1_ADR_O; + wire [15:0] M0_DAT_I, M1_DAT_I; + wire [15:0] M0_DAT_O, M1_DAT_O; + wire M0_STB_O, M1_STB_O; + wire M0_CYC_O, M1_CYC_O; + wire M0_WE_O, M1_WE_O; + wire M0_STALL_I, M1_STALL_I; + + wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; + wire S0_CLK_I, S1_CLK_I, S2_CLK_I, S3_CLK_I; + wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; + wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; + wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; + wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; + wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; + wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; + wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; + + /* Non-wishbone */ + wire M0_finished; + wire M1_finished; + + master_model + #( + .MASTER_NR(0), + .WORD_SIZE(2), + .ADR_BITS(20), + .OPERATIONS_FILE("operations0.mem"), + .OPERATIONS_COUNT(`MASTER0_OPERATIONS_COUNT) + ) master0 + ( + .ACK_I(M0_ACK_I), + .CLK_I(CLK), + .ADR_O(M0_ADR_O), + .DAT_I(M0_DAT_I), + .DAT_O(M0_DAT_O), + .RST_I(RST), + .STB_O(M0_STB_O), + .CYC_O(M0_CYC_O), + .WE_O(M0_WE_O), + .STALL_I(M0_STALL_I), + + .finished(M0_finished) + ); + + master_model + #( + .MASTER_NR(1), + .WORD_SIZE(2), + .ADR_BITS(20), + .OPERATIONS_FILE("operations1.mem"), + .OPERATIONS_COUNT(`MASTER1_OPERATIONS_COUNT) + ) master1 + ( + .ACK_I(M1_ACK_I), + .CLK_I(CLK), + .ADR_O(M1_ADR_O), + .DAT_I(M1_DAT_I), + .DAT_O(M1_DAT_O), + .RST_I(RST), + .STB_O(M1_STB_O), + .CYC_O(M1_CYC_O), + .WE_O(M1_WE_O), + .STALL_I(M1_STALL_I), + + .finished(M1_finished) + ); + + memory_slave_model + #( + .SLAVE_NR(0) + ) slave0 + ( + .ACK_O(S0_ACK_O), + .CLK_I(CLK), + .ADR_I(S0_ADR_I), + .DAT_I(S0_DAT_I), + .DAT_O(S0_DAT_O), + .RST_I(RST), + .STB_I(S0_STB_I), + .WE_I(S0_WE_I), + .STALL_O(S0_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(1) + ) slave1 + ( + .ACK_O(S1_ACK_O), + .CLK_I(CLK), + .ADR_I(S1_ADR_I), + .DAT_I(S1_DAT_I), + .DAT_O(S1_DAT_O), + .RST_I(RST), + .STB_I(S1_STB_I), + .WE_I(S1_WE_I), + .STALL_O(S1_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(2) + ) slave2 + ( + .ACK_O(S2_ACK_O), + .CLK_I(CLK), + .ADR_I(S2_ADR_I), + .DAT_I(S2_DAT_I), + .DAT_O(S2_DAT_O), + .RST_I(RST), + .STB_I(S2_STB_I), + .WE_I(S2_WE_I), + .STALL_O(S2_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(3) + ) slave3 + ( + .ACK_O(S3_ACK_O), + .CLK_I(CLK), + .ADR_I(S3_ADR_I), + .DAT_I(S3_DAT_I), + .DAT_O(S3_DAT_O), + .RST_I(RST), + .STB_I(S3_STB_I), + .WE_I(S3_WE_I), + .STALL_O(S3_STALL_O) + ); + + intercon intercon + ( + .CLK(CLK), + .RST(RST), + + .S0_ACK_O(S0_ACK_O), + .S0_ADR_I(S0_ADR_I), + .S0_DAT_I(S0_DAT_I), + .S0_DAT_O(S0_DAT_O), + .S0_STB_I(S0_STB_I), + .S0_WE_I(S0_WE_I), + .S0_STALL_O(S0_STALL_O), + + .S1_ACK_O(S1_ACK_O), + .S1_ADR_I(S1_ADR_I), + .S1_DAT_I(S1_DAT_I), + .S1_DAT_O(S1_DAT_O), + .S1_STB_I(S1_STB_I), + .S1_WE_I(S1_WE_I), + .S1_STALL_O(S1_STALL_O), + + .S2_ACK_O(S2_ACK_O), + .S2_ADR_I(S2_ADR_I), + .S2_DAT_I(S2_DAT_I), + .S2_DAT_O(S2_DAT_O), + .S2_STB_I(S2_STB_I), + .S2_WE_I(S2_WE_I), + .S2_STALL_O(S2_STALL_O), + + .S3_ACK_O(S3_ACK_O), + .S3_ADR_I(S3_ADR_I), + .S3_DAT_I(S3_DAT_I), + .S3_DAT_O(S3_DAT_O), + .S3_STB_I(S3_STB_I), + .S3_WE_I(S3_WE_I), + .S3_STALL_O(S3_STALL_O), + + .M0_ACK_I(M0_ACK_I), + .M0_ADR_O(M0_ADR_O), + .M0_DAT_I(M0_DAT_I), + .M0_DAT_O(M0_DAT_O), + .M0_STB_O(M0_STB_O), + .M0_CYC_O(M0_CYC_O), + .M0_WE_O(M0_WE_O), + .M0_STALL_I(M0_STALL_I), + + .M1_ACK_I(M1_ACK_I), + .M1_ADR_O(M1_ADR_O), + .M1_DAT_I(M1_DAT_I), + .M1_DAT_O(M1_DAT_O), + .M1_STB_O(M1_STB_O), + .M1_CYC_O(M1_CYC_O), + .M1_WE_O(M1_WE_O), + .M1_STALL_I(M1_STALL_I) + ); + + integer i; + + initial begin + CLK <= 0; + RST <= 1; + + for (i = 0; i < 1000; i++) begin + #1; + + CLK <= ~CLK; + + if (CLK) + RST <= 0; + + if (M0_finished && M1_finished) + $finish; + end + + if (!M0_finished) + $display("error: master 0 hasn't finished its operations in 500 ticks"); + + if (!M1_finished) + $display("error: master 1 hasn't finished its operations in 500 ticks"); + + $finish; + end +endmodule // intercon_test diff --git a/tests/master_arbiter/operations0.memv b/tests/master_arbiter/operations0.memv index bc122b2..b4c48a2 100644 --- a/tests/master_arbiter/operations0.memv +++ b/tests/master_arbiter/operations0.memv @@ -5,14 +5,14 @@ `WRITE(00000, abcd) `WAIT `READ (00000, abcd) -`WRITE(00001, 1234) +`WRITE(50001, 1234) `READ (00000, abcd) `DESELECT `DESELECT -`READ (00001, 1234) -`WRITE(01010, a2a2) -`WRITE(00001, 4321) -`READ (01010, a2a2) +`READ (50001, 1234) +`WRITE(a1010, a2a2) +`WRITE(50001, 4321) +`READ (a1010, a2a2) `WAIT `WAIT `WAIT @@ -25,31 +25,31 @@ `WAIT `DESELECT // Let's force some interleaved single operations by both masters -`WRITE(0001c, 8a9b) +`WRITE(f041c, 8a9b) `DESELECT -`WRITE(0003e, acbd) +`WRITE(b043e, acbd) `DESELECT -`READ (0003e, acbd) +`READ (b043e, acbd) `DESELECT -`READ (0001c, 8a9b) +`READ (f041c, 8a9b) `DESELECT -`WRITE(00050, cedf) +`WRITE(70450, cedf) `DESELECT -`WRITE(00072, e0f1) +`WRITE(00472, e0f1) `DESELECT -`READ (00072, e0f1) +`READ (00472, e0f1) `DESELECT -`READ (00050, cedf) +`READ (70450, cedf) `DESELECT `WAIT -`READ (00001, 4321) +`READ (50001, 4321) // The other master should write the values we check below during its first few // blocks of operations. Although we have no means of synchronizing masters, we // assume, that when 1 of them does a `DESELECT, other one can take over the // bus. Because we do have `DESELECTs above, we can expect at least the first // sets of other master's operations to have completed once we get here. `READ (30000, 03e8) -`READ (30005, 0403) -`READ (30120, 0120) +`READ (50005, 0403) +`READ (50120, 0120) `READ (b0005, 22ef) -`READ (3001a, 0a1b) +`READ (0001a, 0a1b) diff --git a/tests/master_arbiter/operations1.memv b/tests/master_arbiter/operations1.memv index 1900676..57057c2 100644 --- a/tests/master_arbiter/operations1.memv +++ b/tests/master_arbiter/operations1.memv @@ -5,13 +5,13 @@ `WRITE(30000, 03e8) `WAIT `READ (30000, 03e8) -`WRITE(30005, 0403) +`WRITE(50005, 0403) `WAIT `WAIT `WAIT -`WRITE(30120, 0120) -`READ (30005, 0403) -`READ (30120, 0120) +`WRITE(50120, 0120) +`READ (50005, 0403) +`READ (50120, 0120) `DESELECT `WAIT `WAIT @@ -163,28 +163,28 @@ `WAIT `WAIT `READ (b0005, 22ef) -`WRITE(3001a, 0a1b) +`WRITE(0001a, 0a1b) // Only values written until this point will also be checked by master 0 `DESELECT -`READ (3001a, 0a1b) +`READ (0001a, 0a1b) // Let's force some interleaved single operations by both masters -`WRITE(3001c, 0a1b) +`WRITE(4001c, 0a1b) `DESELECT -`WRITE(3003e, 2c3d) +`WRITE(9003e, 2c3d) `DESELECT -`READ (3003e, 2c3d) +`READ (9003e, 2c3d) `DESELECT -`READ (3001c, 0a1b) +`READ (4001c, 0a1b) `DESELECT -`WRITE(30050, 4e5f) +`WRITE(d0050, 4e5f) `DESELECT -`WRITE(30072, 6071) +`WRITE(20072, 6071) `DESELECT -`READ (30072, 6071) +`READ (20072, 6071) `DESELECT -`READ (30050, 4e5f) +`READ (d0050, 4e5f) `DESELECT -// See comment at the end of master 0's operations - we do it analogoulys here +// See comment at the end of master 0's operations - we do it analogously here `READ (00000, abcd) -`READ (01010, a2a2) -`READ (00001, 4321) +`READ (a1010, a2a2) +`READ (50001, 4321) |