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authorWojciech Kosior <kwojtus@protonmail.com>2020-09-08 21:00:13 +0200
committerWojciech Kosior <kwojtus@protonmail.com>2020-09-08 21:00:13 +0200
commitbc43ceac936b48fdccfcac33e172e176273d504f (patch)
treede2723df14a512c214d0fb991a183c363fae042a /tests/stack_machine_store
parentcd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c (diff)
downloadAGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.tar.gz
AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.zip
enable slave and master models to use SEL_ signal
Diffstat (limited to 'tests/stack_machine_store')
-rw-r--r--tests/stack_machine_store/test.v19
1 files changed, 15 insertions, 4 deletions
diff --git a/tests/stack_machine_store/test.v b/tests/stack_machine_store/test.v
index 08230a3..98ea2dc 100644
--- a/tests/stack_machine_store/test.v
+++ b/tests/stack_machine_store/test.v
@@ -36,7 +36,7 @@ module stack_machine_test();
wire [20:0] MD_ADR_O;
wire [31:0] MD_DAT_I;
wire [31:0] MD_DAT_O;
- wire [3:0] MD_SEL_O; /* Ignored for now */
+ wire [3:0] MD_SEL_O;
wire MD_STB_O;
wire MD_CYC_O;
wire MD_WE_O;
@@ -48,6 +48,7 @@ module stack_machine_test();
wire [19:0] SI_ADR_I;
wire [15:0] SI_DAT_I;
wire [15:0] SI_DAT_O;
+ wire SI_SEL_I;
wire SI_RST_I;
wire SI_STB_I;
wire SI_WE_I;
@@ -58,6 +59,7 @@ module stack_machine_test();
wire [20:0] SD_ADR_I;
wire [31:0] SD_DAT_I;
wire [31:0] SD_DAT_O;
+ wire [3:0] SD_SEL_I;
wire SD_RST_I;
wire SD_STB_I;
wire SD_WE_I;
@@ -111,6 +113,7 @@ module stack_machine_test();
.ADR_I(SI_ADR_I),
.DAT_I(SI_DAT_I),
.DAT_O(SI_DAT_O),
+ .SEL_I(SI_SEL_I),
.RST_I(SI_RST_I),
.STB_I(SI_STB_I),
.WE_I(SI_WE_I),
@@ -121,6 +124,7 @@ module stack_machine_test();
#(
.SLAVE_NR(1),
.WORD_SIZE(4),
+ .SEL_LINES(4),
.ADR_BITS(21),
.WRITABLE(1),
.WORDS_TO_INITIALIZE(`INSTRUCTIONS_COUNT),
@@ -132,6 +136,7 @@ module stack_machine_test();
.ADR_I(SD_ADR_I),
.DAT_I(SD_DAT_I),
.DAT_O(SD_DAT_O),
+ .SEL_I(SD_SEL_I),
.RST_I(SD_RST_I),
.STB_I(SD_STB_I),
.WE_I(SD_WE_I),
@@ -155,6 +160,7 @@ module stack_machine_test();
assign SI_CLK_I = CLK;
assign SI_ADR_I = MI_ADR_O;
assign SI_DAT_I = MI_DAT_O;
+ assign SI_SEL_I = 1;
assign SI_RST_I = RST;
assign SI_STB_I = MI_STB_O && MI_CYC_O;
assign SI_WE_I = MI_WE_O;
@@ -162,6 +168,7 @@ module stack_machine_test();
assign SD_CLK_I = CLK;
assign SD_ADR_I = MD_ADR_O;
assign SD_DAT_I = MD_DAT_O;
+ assign SD_SEL_I = MD_SEL_O;
assign SD_RST_I = RST;
assign SD_STB_I = MD_STB_O && MD_CYC_O;
assign SD_WE_I = MD_WE_O;
@@ -169,6 +176,7 @@ module stack_machine_test();
integer i, j;
reg [21:0] address;
reg [31:0] expected_value;
+ reg [31:0] found_value;
reg [31:0] words_to_verify[`WORDS_TO_VERIFY_COUNT * 2 - 1 : 0];
@@ -189,12 +197,15 @@ module stack_machine_test();
0, `WORDS_TO_VERIFY_COUNT * 2 - 1);
for (j = 0; j < `WORDS_TO_VERIFY_COUNT; j++) begin
- /* Keep in mind we haven't implemented byte-grained access yet */
address = words_to_verify[2 * j][21:0];
+ found_value = {slave_D.memory[address + 3],
+ slave_D.memory[address + 2],
+ slave_D.memory[address + 1],
+ slave_D.memory[address]};
expected_value = words_to_verify[2 * j + 1];
- if (slave_D.memory[address] !== expected_value) begin
+ if (found_value !== expected_value) begin
`MSG(("error: expected h%x at h%x, but got h%x",
- expected_value, address, slave_D.memory[address]));
+ expected_value, address, found_value));
end
end