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author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-07 21:24:51 +0200 |
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committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-07 21:24:51 +0200 |
commit | 16d285dac3271becd7a20ccd434c8f4deceeec4a (patch) | |
tree | 973fc9a0183e31c9c66183fe4ff92c79df7eaede /tests/stack_machine_old_store/test.v | |
parent | bf735fa64184033131c17b13d457a1313c2846e2 (diff) | |
download | AGH-engineering-thesis-16d285dac3271becd7a20ccd434c8f4deceeec4a.tar.gz AGH-engineering-thesis-16d285dac3271becd7a20ccd434c8f4deceeec4a.zip |
remove old version of stack machine from the project
Diffstat (limited to 'tests/stack_machine_old_store/test.v')
-rw-r--r-- | tests/stack_machine_old_store/test.v | 140 |
1 files changed, 0 insertions, 140 deletions
diff --git a/tests/stack_machine_old_store/test.v b/tests/stack_machine_old_store/test.v deleted file mode 100644 index 7e7429f..0000000 --- a/tests/stack_machine_old_store/test.v +++ /dev/null @@ -1,140 +0,0 @@ -`default_nettype none - -`include "messages.vh" - -`ifndef SIMULATION - `error_SIMULATION_not_defined -; /* Cause syntax error */ -`endif - -`ifndef INSTRUCTIONS_COUNT - `error_INSTRUCTIONS_COUNT_must_be_defined -; /* Cause syntax error */ -`endif - -`ifndef WORDS_TO_VERIFY_COUNT - `error_WORDS_TO_VERIFY_COUNT_must_be_defined -; /* Cause syntax error */ -`endif - -module stack_machine_test(); - wire M_ACK_I; - wire M_CLK_I; - wire [19:0] M_ADR_O; - wire [15:0] M_DAT_I; - wire [15:0] M_DAT_O; - wire M_RST_I; - wire M_STB_O; - wire M_CYC_O; - wire M_WE_O; - wire M_STALL_I; - - wire S_ACK_O; - wire S_CLK_I; - wire [17:0] S_ADR_I; - wire [15:0] S_DAT_I; - wire [15:0] S_DAT_O; - wire S_RST_I; - wire S_STB_I; - wire S_WE_I; - wire S_STALL_O; - - /* Non-wishbone */ - wire M_finished; - - stack_machine stack_machine - ( - .ACK_I(M_ACK_I), - .CLK_I(M_CLK_I), - .ADR_O(M_ADR_O), - .DAT_I(M_DAT_I), - .DAT_O(M_DAT_O), - .RST_I(M_RST_I), - .STB_O(M_STB_O), - .CYC_O(M_CYC_O), - .WE_O(M_WE_O), - .STALL_I(M_STALL_I), - - .finished(M_finished) - ); - - memory_slave_model - #( - .SLAVE_NR(0), - .WRITABLE(1), - .WORDS_TO_INITIALIZE(`INSTRUCTIONS_COUNT), - .INITIAL_CONTENTS_FILE("instructions.mem") - ) slave - ( - .ACK_O(S_ACK_O), - .CLK_I(S_CLK_I), - .ADR_I(S_ADR_I), - .DAT_I(S_DAT_I), - .DAT_O(S_DAT_O), - .RST_I(S_RST_I), - .STB_I(S_STB_I), - .WE_I(S_WE_I), - .STALL_O(S_STALL_O) - ); - - reg CLK; - reg RST; - - assign M_ACK_I = S_ACK_O; - assign M_CLK_I = CLK; - assign M_DAT_I = S_DAT_O; - assign M_RST_I = RST; - assign M_STALL_I = S_STALL_O; - - assign S_CLK_I = CLK; - assign S_ADR_I = M_ADR_O[17:0]; /* Ignore 2 topmost bits */ - assign S_DAT_I = M_DAT_O; - assign S_RST_I = RST; - assign S_STB_I = M_STB_O && M_CYC_O; - assign S_WE_I = M_WE_O; - - integer i, j; - reg [17:0] address; - reg [15:0] expected_value; - - reg [19:0] words_to_verify[`WORDS_TO_VERIFY_COUNT * 2 - 1 : 0]; - - initial begin - CLK <= 0; - RST <= 1; - - for (i = 0; i < 3500; i++) begin - #1; - - CLK <= ~CLK; - - if (CLK) - RST <= 0; - - if (M_finished) begin - $readmemh("words_to_verify.mem", words_to_verify, - 0, `WORDS_TO_VERIFY_COUNT * 2 - 1); - - for (j = 0; j < `WORDS_TO_VERIFY_COUNT; j++) begin - /* - * Byte-grained addresses are used in CPU, and we also use - * them in tclasm opcodes and in files with words for - * verification. Slaves and wishbone address 16-bit words, not - * single bytes. We need to drop the lowest bit here. - */ - address = words_to_verify[2 * j][19:1]; - expected_value = words_to_verify[2 * j + 1]; - if (slave.memory[address] !== expected_value) begin - `MSG(("error: expected h%x at h%x, but got h%x", - expected_value, address, slave.memory[address])); - end - end - - $finish; - end // if (M_finished) - end // for (i = 0; i < 3500; i++) - - $display("error: cpu hasn't finished its operations in 1750 ticks"); - $finish; - end // initial begin -endmodule // stack_machine_test |