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author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-01 10:54:59 +0200 |
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committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-01 11:04:22 +0200 |
commit | ee1f6c47e1eff920068f4bceaf604f9535a2e8a9 (patch) | |
tree | 580eb001a72601d254bb29cc348a529490f84808 /tests/self | |
parent | cd02ddff8886aa1db29f80d3cc5cf99a349d8258 (diff) | |
download | AGH-engineering-thesis-ee1f6c47e1eff920068f4bceaf604f9535a2e8a9.tar.gz AGH-engineering-thesis-ee1f6c47e1eff920068f4bceaf604f9535a2e8a9.zip |
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Diffstat (limited to 'tests/self')
-rw-r--r-- | tests/self/operations.memv | 25 | ||||
-rw-r--r-- | tests/self/test.v | 114 |
2 files changed, 139 insertions, 0 deletions
diff --git a/tests/self/operations.memv b/tests/self/operations.memv new file mode 100644 index 0000000..5769d94 --- /dev/null +++ b/tests/self/operations.memv @@ -0,0 +1,25 @@ +`include "macroasm.vh" // look into macroasm.vh for more info + +`WRITE(00000, abcd) +`WAIT +`READ (00000, abcd) +`WRITE(00001, 1234) +`READ (00000, abcd) +`DESELECT +`DESELECT +`READ (00001, 1234) +`WRITE(01010, a2a2) +`WRITE(00001, 4321) +`READ (01010, a2a2) +`WAIT +`WAIT +`WAIT +`WAIT +`WAIT +`DESELECT +`DESELECT +`DESELECT +`WAIT +`DESELECT +`WAIT +`READ(00001, 4321) diff --git a/tests/self/test.v b/tests/self/test.v new file mode 100644 index 0000000..b92a63e --- /dev/null +++ b/tests/self/test.v @@ -0,0 +1,114 @@ +`default_nettype none + +`include "messages.vh" + +`ifndef MASTER_OPERATIONS_COUNT + `error_MASTER_OPERATIONS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + +`ifndef SIMULATION + `error_SIMULATION_not_defined +; /* Cause syntax error */ +`endif + +module self_test(); + wire M_ACK_I; + wire M_CLK_I; + wire [19:0] M_ADR_O; + wire [15:0] M_DAT_I; + wire [15:0] M_DAT_O; + wire M_RST_I; + wire M_STB_O; + wire M_CYC_O; + wire M_WE_O; + wire M_STALL_I; + + wire S_ACK_O; + wire S_CLK_I; + wire [17:0] S_ADR_I; + wire [15:0] S_DAT_I; + wire [15:0] S_DAT_O; + wire S_RST_I; + wire S_STB_I; + wire S_WE_I; + wire S_STALL_O; + + /* Non-wishbone */ + wire M_finished; + + master_model + #( + .MASTER_NR(0), + .OPERATIONS_FILE("operations.mem"), + .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT) + ) master + ( + .ACK_I(M_ACK_I), + .CLK_I(M_CLK_I), + .ADR_O(M_ADR_O), + .DAT_I(M_DAT_I), + .DAT_O(M_DAT_O), + .RST_I(M_RST_I), + .STB_O(M_STB_O), + .CYC_O(M_CYC_O), + .WE_O(M_WE_O), + .STALL_I(M_STALL_I), + + .finished(M_finished) + ); + + memory_slave_model + #( + .SLAVE_NR(0) + ) slave + ( + .ACK_O(S_ACK_O), + .CLK_I(S_CLK_I), + .ADR_I(S_ADR_I), + .DAT_I(S_DAT_I), + .DAT_O(S_DAT_O), + .RST_I(S_RST_I), + .STB_I(S_STB_I), + .WE_I(S_WE_I), + .STALL_O(S_STALL_O) + ); + + reg CLK; + reg RST; + + assign M_ACK_I = S_ACK_O; + assign M_CLK_I = CLK; + assign M_DAT_I = S_DAT_O; + assign M_RST_I = RST; + assign M_STALL_I = S_STALL_O; + + assign S_CLK_I = CLK; + assign S_ADR_I = M_ADR_O[17:0]; /* Ignore 2 topmost bits */ + assign S_DAT_I = M_DAT_O; + assign S_RST_I = RST; + assign S_STB_I = M_STB_O && M_CYC_O; + assign S_WE_I = M_WE_O; + + integer i; + + initial begin + CLK <= 0; + RST <= 1; + + for (i = 0; i < 600; i++) begin + #1; + + CLK <= ~CLK; + + if (CLK) + RST <= 0; + + if (M_finished) + $finish; + end + + $display("error: master hasn't finished its operations in 300 ticks"); + $finish; + end +endmodule // self_test |