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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 21:00:13 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 21:00:13 +0200 |
| commit | bc43ceac936b48fdccfcac33e172e176273d504f (patch) | |
| tree | de2723df14a512c214d0fb991a183c363fae042a /tests/self | |
| parent | cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c (diff) | |
| download | AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.tar.gz AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.zip | |
enable slave and master models to use SEL_ signal
Diffstat (limited to 'tests/self')
| -rw-r--r-- | tests/self/test.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/self/test.v b/tests/self/test.v index 8eb0617..323dba2 100644 --- a/tests/self/test.v +++ b/tests/self/test.v @@ -18,6 +18,7 @@ module self_test(); wire [19:0] M_ADR_O; wire [15:0] M_DAT_I; wire [15:0] M_DAT_O; + wire M_SEL_O; /* Always high in this test */ wire M_RST_I; wire M_STB_O; wire M_CYC_O; @@ -29,6 +30,7 @@ module self_test(); wire [17:0] S_ADR_I; wire [15:0] S_DAT_I; wire [15:0] S_DAT_O; + wire S_SEL_I; /* Always high in this test */ wire S_RST_I; wire S_STB_I; wire S_WE_I; @@ -49,6 +51,7 @@ module self_test(); .ADR_O(M_ADR_O), .DAT_I(M_DAT_I), .DAT_O(M_DAT_O), + .SEL_O(M_SEL_O), .RST_I(M_RST_I), .STB_O(M_STB_O), .CYC_O(M_CYC_O), @@ -68,6 +71,7 @@ module self_test(); .ADR_I(S_ADR_I), .DAT_I(S_DAT_I), .DAT_O(S_DAT_O), + .SEL_I(S_SEL_I), .RST_I(S_RST_I), .STB_I(S_STB_I), .WE_I(S_WE_I), @@ -86,6 +90,7 @@ module self_test(); assign S_CLK_I = CLK; assign S_ADR_I = M_ADR_O[17:0]; /* Ignore 2 topmost bits */ assign S_DAT_I = M_DAT_O; + assign S_SEL_I = M_SEL_O; assign S_RST_I = RST; assign S_STB_I = M_STB_O && M_CYC_O; assign S_WE_I = M_WE_O; |