add intercon module, that encapsulates slave_dispatcher and master_arbiter and a bench for it (use adapted operations files from master_arbiter test)

2 files changed, 34 insertions, 34 deletions

diff --git a/tests/master_arbiter/operations0.memv b/tests/master_arbiter/operations0.memv
index bc122b2..b4c48a2 100644
--- a/tests/master_arbiter/operations0.memv
+++ b/tests/master_arbiter/operations0.memv
@@ -5,14 +5,14 @@
 `WRITE(00000, abcd)
 `WAIT
 `READ (00000, abcd)
-`WRITE(00001, 1234)
+`WRITE(50001, 1234)
 `READ (00000, abcd)
 `DESELECT
 `DESELECT
-`READ (00001, 1234)
-`WRITE(01010, a2a2)
-`WRITE(00001, 4321)
-`READ (01010, a2a2)
+`READ (50001, 1234)
+`WRITE(a1010, a2a2)
+`WRITE(50001, 4321)
+`READ (a1010, a2a2)
 `WAIT
 `WAIT
 `WAIT
@@ -25,31 +25,31 @@
 `WAIT
 `DESELECT
 // Let's force some interleaved single operations by both masters
-`WRITE(0001c, 8a9b)
+`WRITE(f041c, 8a9b)
 `DESELECT
-`WRITE(0003e, acbd)
+`WRITE(b043e, acbd)
 `DESELECT
-`READ (0003e, acbd)
+`READ (b043e, acbd)
 `DESELECT
-`READ (0001c, 8a9b)
+`READ (f041c, 8a9b)
 `DESELECT
-`WRITE(00050, cedf)
+`WRITE(70450, cedf)
 `DESELECT
-`WRITE(00072, e0f1)
+`WRITE(00472, e0f1)
 `DESELECT
-`READ (00072, e0f1)
+`READ (00472, e0f1)
 `DESELECT
-`READ (00050, cedf)
+`READ (70450, cedf)
 `DESELECT
 `WAIT
-`READ (00001, 4321)
+`READ (50001, 4321)
 // The other master should write the values we check below during its first few
 // blocks of operations. Although we have no means of synchronizing masters, we
 // assume, that when 1 of them does a `DESELECT, other one can take over the
 // bus. Because we do have `DESELECTs above, we can expect at least the first
 // sets of other master's operations to have completed once we get here.
 `READ (30000, 03e8)
-`READ (30005, 0403)
-`READ (30120, 0120)
+`READ (50005, 0403)
+`READ (50120, 0120)
 `READ (b0005, 22ef)
-`READ (3001a, 0a1b)
+`READ (0001a, 0a1b)
diff --git a/tests/master_arbiter/operations1.memv b/tests/master_arbiter/operations1.memv
index 1900676..57057c2 100644
--- a/tests/master_arbiter/operations1.memv
+++ b/tests/master_arbiter/operations1.memv
@@ -5,13 +5,13 @@
 `WRITE(30000, 03e8)
 `WAIT
 `READ (30000, 03e8)
-`WRITE(30005, 0403)
+`WRITE(50005, 0403)
 `WAIT
 `WAIT
 `WAIT
-`WRITE(30120, 0120)
-`READ (30005, 0403)
-`READ (30120, 0120)
+`WRITE(50120, 0120)
+`READ (50005, 0403)
+`READ (50120, 0120)
 `DESELECT
 `WAIT
 `WAIT
@@ -163,28 +163,28 @@
 `WAIT
 `WAIT
 `READ (b0005, 22ef)
-`WRITE(3001a, 0a1b)
+`WRITE(0001a, 0a1b)
 // Only values written until this point will also be checked by master 0
 `DESELECT
-`READ (3001a, 0a1b)
+`READ (0001a, 0a1b)
 // Let's force some interleaved single operations by both masters
-`WRITE(3001c, 0a1b)
+`WRITE(4001c, 0a1b)
 `DESELECT
-`WRITE(3003e, 2c3d)
+`WRITE(9003e, 2c3d)
 `DESELECT
-`READ (3003e, 2c3d)
+`READ (9003e, 2c3d)
 `DESELECT
-`READ (3001c, 0a1b)
+`READ (4001c, 0a1b)
 `DESELECT
-`WRITE(30050, 4e5f)
+`WRITE(d0050, 4e5f)
 `DESELECT
-`WRITE(30072, 6071)
+`WRITE(20072, 6071)
 `DESELECT
-`READ (30072, 6071)
+`READ (20072, 6071)
 `DESELECT
-`READ (30050, 4e5f)
+`READ (d0050, 4e5f)
 `DESELECT
-// See comment at the end of master 0's operations - we do it analogoulys here
+// See comment at the end of master 0's operations - we do it analogously here
 `READ (00000, abcd)
-`READ (01010, a2a2)
-`READ (00001, 4321)
+`READ (a1010, a2a2)
+`READ (50001, 4321)