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author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 21:00:13 +0200 |
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committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 21:00:13 +0200 |
commit | bc43ceac936b48fdccfcac33e172e176273d504f (patch) | |
tree | de2723df14a512c214d0fb991a183c363fae042a /tests/master_arbiter/test.v | |
parent | cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c (diff) | |
download | AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.tar.gz AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.zip |
enable slave and master models to use SEL_ signal
Diffstat (limited to 'tests/master_arbiter/test.v')
-rw-r--r-- | tests/master_arbiter/test.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/master_arbiter/test.v b/tests/master_arbiter/test.v index bcf90b8..58e3add 100644 --- a/tests/master_arbiter/test.v +++ b/tests/master_arbiter/test.v @@ -22,6 +22,7 @@ module master_arbiter_test(); wire [19:0] M0_ADR_O; wire [15:0] M0_DAT_I; wire [15:0] M0_DAT_O; + wire M0_SEL_O; /* Ignored, assumed always high */ wire M0_STB_O; wire M0_CYC_O; wire M0_WE_O; @@ -31,6 +32,7 @@ module master_arbiter_test(); wire [19:0] M1_ADR_O; wire [15:0] M1_DAT_I; wire [15:0] M1_DAT_O; + wire M1_SEL_O; /* Ignored, assumed always high */ wire M1_STB_O; wire M1_CYC_O; wire M1_WE_O; @@ -40,6 +42,7 @@ module master_arbiter_test(); wire [19:0] S_ADR_I; wire [15:0] S_DAT_I; wire [15:0] S_DAT_O; + wire S_SEL_I; /* Always high */ wire S_STB_I; wire S_WE_I; wire S_STALL_O; @@ -76,6 +79,7 @@ module master_arbiter_test(); .ADR_O(M0_ADR_O), .DAT_I(M0_DAT_I), .DAT_O(M0_DAT_O), + .SEL_O(M0_SEL_O), .RST_I(RST), .STB_O(M0_STB_O), .CYC_O(M0_CYC_O), @@ -99,6 +103,7 @@ module master_arbiter_test(); .ADR_O(M1_ADR_O), .DAT_I(M1_DAT_I), .DAT_O(M1_DAT_O), + .SEL_O(M1_SEL_O), .RST_I(RST), .STB_O(M1_STB_O), .CYC_O(M1_CYC_O), @@ -120,6 +125,7 @@ module master_arbiter_test(); .ADR_I(S_ADR_I), .DAT_I(S_DAT_I), .DAT_O(S_DAT_O), + .SEL_I(S_SEL_I), .RST_I(RST), .STB_I(S_STB_I), .WE_I(S_WE_I), @@ -165,6 +171,7 @@ module master_arbiter_test(); assign S_ADR_I = M_COMBINED_ADR_O[19:0]; assign S_DAT_I = M_COMBINED_DAT_O; + assign S_SEL_I = 1; assign S_STB_I = M_COMBINED_STB_O && M_COMBINED_CYC_O; assign S_WE_I = M_COMBINED_WE_O; |