enable slave and master models to use SEL_ signal

1 files changed, 6 insertions, 3 deletions

diff --git a/tests/interface_wrapper/test.v b/tests/interface_wrapper/test.v
index cbd3d88..4031f35 100644
--- a/tests/interface_wrapper/test.v
+++ b/tests/interface_wrapper/test.v
@@ -22,7 +22,7 @@ module interface_wrapper_test();
    wire [20:0] M_RAW_ADR_O;
    wire [31:0] M_RAW_DAT_I;
    wire [31:0] M_RAW_DAT_O;
-   wire [3:0]  M_RAW_SEL_O; /* Not used yet, always 4'hF */
+   wire [3:0]  M_RAW_SEL_O; /* This is being worked on */
    wire        M_RAW_STB_O;
    wire        M_RAW_CYC_O;
    wire        M_RAW_WE_O;
@@ -42,6 +42,7 @@ module interface_wrapper_test();
    wire [19:0] S_ADR_I;
    wire [15:0] S_DAT_I;
    wire [15:0] S_DAT_O;
+   wire        S_SEL_I; /* Always high */
    wire        S_RST_I;
    wire        S_STB_I;
    wire        S_WE_I;
@@ -54,6 +55,7 @@ module interface_wrapper_test();
      #(
        .MASTER_NR(0),
        .WORD_SIZE(4),
+       .SEL_LINES(4),
        .ADR_BITS(21),
        .OPERATIONS_FILE("operations.mem"),
        .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT)
@@ -64,6 +66,7 @@ module interface_wrapper_test();
 	.ADR_O(M_RAW_ADR_O),
 	.DAT_I(M_RAW_DAT_I),
 	.DAT_O(M_RAW_DAT_O),
+	.SEL_O(M_RAW_SEL_O),
  	.RST_I(M_RST_I),
 	.STB_O(M_RAW_STB_O),
 	.CYC_O(M_RAW_CYC_O),
@@ -85,6 +88,7 @@ module interface_wrapper_test();
 	.ADR_I(S_ADR_I),
 	.DAT_I(S_DAT_I),
 	.DAT_O(S_DAT_O),
+	.SEL_I(S_SEL_I),
       	.RST_I(S_RST_I),
       	.STB_I(S_STB_I),
       	.WE_I(S_WE_I),
@@ -127,11 +131,10 @@ interface_wrapper wrapper
    assign M_WRAPPED_DAT_I = S_DAT_O;
    assign M_WRAPPED_STALL_I = S_STALL_O;
 
-   assign M_RAW_SEL_O = 4'hF;
-
    assign S_CLK_I = CLK;
    assign S_ADR_I = M_WRAPPED_ADR_O;
    assign S_DAT_I = M_WRAPPED_DAT_O;
+   assign S_SEL_I = 1;
    assign S_RST_I = RST;
    assign S_STB_I = M_WRAPPED_STB_O && M_WRAPPED_CYC_O;
    assign S_WE_I = M_WRAPPED_WE_O;