start anew

2 files changed, 279 insertions, 0 deletions

diff --git a/tests/intercon/operations.memv b/tests/intercon/operations.memv
new file mode 100644
index 0000000..8785d5c
--- /dev/null
+++ b/tests/intercon/operations.memv
@@ -0,0 +1,63 @@
+`include "macroasm.vh" // look into macroasm.vh for more info
+
+// The beginning copied from self test, only 1st slave is being accessed.
+`WRITE(00000, abcd)
+`WAIT
+`READ (00000, abcd)
+`WRITE(00001, 1234)
+`READ (00000, abcd)
+`DESELECT
+`DESELECT
+`READ (00001, 1234)
+`WRITE(01010, a2a2)
+`WRITE(00001, 4321)
+`READ (01010, a2a2)
+`WAIT
+`WAIT
+`WAIT
+`WAIT
+`WAIT
+`DESELECT
+`DESELECT
+`DESELECT
+`WAIT
+`DESELECT
+`WAIT
+`READ(00001, 4321)
+// Here, instructions targetting other slaves start appearing.
+// Go through all the slaves
+`WRITE(40040, efef)
+`WRITE(80002, 1f1f)
+`WRITE(c00c0, 1d1d)
+`READ (80002, 1f1f)
+`READ (c00c0, 1d1d)
+`READ (40040, efef)
+`WAIT
+`WAIT
+// Make a sequence of commands to slave 3 (addresses c0000 - fffff)
+`READ (c00c0, 1d1d)
+`WRITE(c1111, 0022)
+`READ (c00c0, 1d1d)
+`WRITE(c0001, 0001)
+`WRITE(c0002, 0002)
+`READ (c0001, 0001)
+`READ (c0002, 0002)
+`READ (c0001, 0001)
+`WRITE(c0003, 0003)
+`WRITE(c0002, 2222)
+`READ (c0002, 2222)
+`READ (c0003, 0003)
+`WRITE(fffff, 5555)
+`READ (c1111, 0022)
+// Put a single command to another slave in-between commands to slave 3
+`WRITE(4ffff, b6b6)
+`READ (fffff, 5555)
+`WRITE(eeeee, aaaa)
+`READ (eeeee, aaaa)
+// Let slave 3 take a breath now
+`READ (4ffff, b6b6)
+`DESELECT
+// We made writes to c0002 and c0001, make sure corresponding addreses
+// in other slaves were not overwritten by mistake
+`READ (80002, 1f1f)
+`READ (00001, 4321)
diff --git a/tests/intercon/test.v b/tests/intercon/test.v
new file mode 100644
index 0000000..1945f44
--- /dev/null
+++ b/tests/intercon/test.v
@@ -0,0 +1,216 @@
+`default_nettype none
+
+`include "messages.vh"
+
+`ifndef MASTER_OPERATIONS_COUNT
+ `error_MASTER_OPERATIONS_COUNT_must_be_defined
+; /* Cause syntax error */
+`endif
+
+`ifndef SIMULATION
+ `error_SIMULATION_not_defined
+; /* Cause syntax error */
+`endif
+
+module intercon_test();
+   wire        M_ACK_I;
+   wire        M_CLK_I;
+   wire [19:0] M_ADR_O;
+   wire [15:0] M_DAT_I;
+   wire [15:0] M_DAT_O;
+   wire        M_RST_I;
+   wire        M_STB_O;
+   wire        M_CYC_O;
+   wire        M_WE_O;
+   wire        M_STALL_I;
+
+   wire        S0_ACK_O,   S1_ACK_O,   S2_ACK_O,   S3_ACK_O;
+   wire        S0_CLK_I,   S1_CLK_I,   S2_CLK_I,   S3_CLK_I;
+   wire [17:0] S0_ADR_I,   S1_ADR_I,   S2_ADR_I,   S3_ADR_I;
+   wire [15:0] S0_DAT_I,   S1_DAT_I,   S2_DAT_I,   S3_DAT_I;
+   wire [15:0] S0_DAT_O,   S1_DAT_O,   S2_DAT_O,   S3_DAT_O;
+   wire        S0_RST_I,   S1_RST_I,   S2_RST_I,   S3_RST_I;
+   wire        S0_STB_I,   S1_STB_I,   S2_STB_I,   S3_STB_I;
+   wire        S0_WE_I,    S1_WE_I,    S2_WE_I,    S3_WE_I;
+   wire        S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O;
+
+   reg 	       CLK;
+   reg 	       RST;
+
+   /* Non-wishbone */
+   wire        M_finished;
+
+   master_model
+     #(.MASTER_NR(0),
+       .OPERATIONS_FILE("operations.mem"),
+       .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT)
+       ) master
+       (
+	.ACK_I(M_ACK_I),
+ 	.CLK_I(M_CLK_I),
+	.ADR_O(M_ADR_O),
+	.DAT_I(M_DAT_I),
+	.DAT_O(M_DAT_O),
+ 	.RST_I(M_RST_I),
+	.STB_O(M_STB_O),
+	.CYC_O(M_CYC_O),
+	.WE_O(M_WE_O),
+ 	.STALL_I(M_STALL_I),
+
+	.finished(M_finished)
+	);
+
+   memory_slave_model
+     #(
+       .SLAVE_NR(0)
+       ) slave0
+       (
+	.ACK_O(S0_ACK_O),
+      	.CLK_I(S0_CLK_I),
+	.ADR_I(S0_ADR_I),
+	.DAT_I(S0_DAT_I),
+	.DAT_O(S0_DAT_O),
+      	.RST_I(S0_RST_I),
+      	.STB_I(S0_STB_I),
+      	.WE_I(S0_WE_I),
+	.STALL_O(S0_STALL_O)
+	);
+
+   memory_slave_model
+     #(
+       .SLAVE_NR(1)
+       ) slave1
+       (
+	.ACK_O(S1_ACK_O),
+      	.CLK_I(S1_CLK_I),
+	.ADR_I(S1_ADR_I),
+	.DAT_I(S1_DAT_I),
+	.DAT_O(S1_DAT_O),
+      	.RST_I(S1_RST_I),
+      	.STB_I(S1_STB_I),
+      	.WE_I(S1_WE_I),
+	.STALL_O(S1_STALL_O)
+	);
+
+   memory_slave_model
+     #(
+       .SLAVE_NR(2)
+       ) slave2
+       (
+	.ACK_O(S2_ACK_O),
+      	.CLK_I(S2_CLK_I),
+	.ADR_I(S2_ADR_I),
+	.DAT_I(S2_DAT_I),
+	.DAT_O(S2_DAT_O),
+      	.RST_I(S2_RST_I),
+      	.STB_I(S2_STB_I),
+      	.WE_I(S2_WE_I),
+	.STALL_O(S2_STALL_O)
+	);
+
+   memory_slave_model
+     #(
+       .SLAVE_NR(3)
+       ) slave3
+       (
+	.ACK_O(S3_ACK_O),
+      	.CLK_I(S3_CLK_I),
+	.ADR_I(S3_ADR_I),
+	.DAT_I(S3_DAT_I),
+	.DAT_O(S3_DAT_O),
+      	.RST_I(S3_RST_I),
+      	.STB_I(S3_STB_I),
+      	.WE_I(S3_WE_I),
+	.STALL_O(S3_STALL_O)
+	);
+
+   intercon intercon
+     (
+      .CLK(CLK),
+      .RST(RST),
+
+      .S0_ACK_O(S0_ACK_O),
+      .S0_CLK_I(S0_CLK_I),
+      .S0_ADR_I(S0_ADR_I),
+      .S0_DAT_I(S0_DAT_I),
+      .S0_DAT_O(S0_DAT_O),
+      .S0_RST_I(S0_RST_I),
+      .S0_STB_I(S0_STB_I),
+      .S0_WE_I(S0_WE_I),
+      .S0_STALL_O(S0_STALL_O),
+
+      .S1_ACK_O(S1_ACK_O),
+      .S1_CLK_I(S1_CLK_I),
+      .S1_ADR_I(S1_ADR_I),
+      .S1_DAT_I(S1_DAT_I),
+      .S1_DAT_O(S1_DAT_O),
+      .S1_RST_I(S1_RST_I),
+      .S1_STB_I(S1_STB_I),
+      .S1_WE_I(S1_WE_I),
+      .S1_STALL_O(S1_STALL_O),
+
+      .S2_ACK_O(S2_ACK_O),
+      .S2_CLK_I(S2_CLK_I),
+      .S2_ADR_I(S2_ADR_I),
+      .S2_DAT_I(S2_DAT_I),
+      .S2_DAT_O(S2_DAT_O),
+      .S2_RST_I(S2_RST_I),
+      .S2_STB_I(S2_STB_I),
+      .S2_WE_I(S2_WE_I),
+      .S2_STALL_O(S2_STALL_O),
+
+      .S3_ACK_O(S3_ACK_O),
+      .S3_CLK_I(S3_CLK_I),
+      .S3_ADR_I(S3_ADR_I),
+      .S3_DAT_I(S3_DAT_I),
+      .S3_DAT_O(S3_DAT_O),
+      .S3_RST_I(S3_RST_I),
+      .S3_STB_I(S3_STB_I),
+      .S3_WE_I(S3_WE_I),
+      .S3_STALL_O(S3_STALL_O),
+
+      .M_ACK_I(M_ACK_I),
+      .M_CLK_I(M_CLK_I),
+      .M_ADR_O(M_ADR_O),
+      .M_DAT_O(M_DAT_O),
+      .M_DAT_I(M_DAT_I),
+      .M_RST_I(M_RST_I),
+      .M_STB_O(M_STB_O),
+      .M_CYC_O(M_CYC_O),
+      .M_WE_O(M_WE_O),
+      .M_STALL_I(M_STALL_I)
+      );
+
+   integer     i;
+
+   initial begin
+      CLK <= 0;
+      RST <= 1;
+
+      for (i = 0; i < 500; i++) begin
+	 #1;
+
+	 CLK <= ~CLK;
+
+	 if (CLK)
+	   RST <= 0;
+
+	 if (M_finished)
+	   $finish;
+
+	 /*
+	  * I should delete this debugging code, but from time to time
+	  * it proves so handy, that I just can't do it :/
+	  */
+	 // if (!CLK)
+	 //   `DBG(({"M_CYC_O: %d   M_STB_O: %d   M_ACK_I: %d   M_STALL_I: %d   ",
+	 //  	  "sla: %d   sa: %d   ca: %d   RST: %b"},
+	 //  	 M_CYC_O, M_STB_O, M_ACK_I, M_STALL_I,
+	 //  	 intercon.slave_last_accessed, intercon.slave_accessed,
+	 // 	 intercon.commands_awaiting, intercon.RST));
+      end
+
+      $display("error: master hasn't finished its opertaions in 300 ticks");
+      $finish;
+   end
+endmodule // intercon_test