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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 21:00:13 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 21:00:13 +0200 |
| commit | bc43ceac936b48fdccfcac33e172e176273d504f (patch) | |
| tree | de2723df14a512c214d0fb991a183c363fae042a /tests/intercon | |
| parent | cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c (diff) | |
| download | AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.tar.gz AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.zip | |
enable slave and master models to use SEL_ signal
Diffstat (limited to 'tests/intercon')
| -rw-r--r-- | tests/intercon/test.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/intercon/test.v b/tests/intercon/test.v index 313f4c6..f2102a6 100644 --- a/tests/intercon/test.v +++ b/tests/intercon/test.v @@ -25,6 +25,7 @@ module intercon_test(); wire [19:0] M0_ADR_O, M1_ADR_O; wire [15:0] M0_DAT_I, M1_DAT_I; wire [15:0] M0_DAT_O, M1_DAT_O; + wire M0_SEL_O, M1_SEL_O; /* Ignored, assumed always high */ wire M0_STB_O, M1_STB_O; wire M0_CYC_O, M1_CYC_O; wire M0_WE_O, M1_WE_O; @@ -35,6 +36,7 @@ module intercon_test(); wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; + wire S0_SEL_I, S1_SEL_I, S2_SEL_I, S3_SEL_I; /* Always high */ wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; @@ -58,6 +60,7 @@ module intercon_test(); .ADR_O(M0_ADR_O), .DAT_I(M0_DAT_I), .DAT_O(M0_DAT_O), + .SEL_O(M0_SEL_O), .RST_I(RST), .STB_O(M0_STB_O), .CYC_O(M0_CYC_O), @@ -81,6 +84,7 @@ module intercon_test(); .ADR_O(M1_ADR_O), .DAT_I(M1_DAT_I), .DAT_O(M1_DAT_O), + .SEL_O(M1_SEL_O), .RST_I(RST), .STB_O(M1_STB_O), .CYC_O(M1_CYC_O), @@ -100,6 +104,7 @@ module intercon_test(); .ADR_I(S0_ADR_I), .DAT_I(S0_DAT_I), .DAT_O(S0_DAT_O), + .SEL_I(S0_SEL_I), .RST_I(RST), .STB_I(S0_STB_I), .WE_I(S0_WE_I), @@ -116,6 +121,7 @@ module intercon_test(); .ADR_I(S1_ADR_I), .DAT_I(S1_DAT_I), .DAT_O(S1_DAT_O), + .SEL_I(S1_SEL_I), .RST_I(RST), .STB_I(S1_STB_I), .WE_I(S1_WE_I), @@ -132,6 +138,7 @@ module intercon_test(); .ADR_I(S2_ADR_I), .DAT_I(S2_DAT_I), .DAT_O(S2_DAT_O), + .SEL_I(S2_SEL_I), .RST_I(RST), .STB_I(S2_STB_I), .WE_I(S2_WE_I), @@ -148,6 +155,7 @@ module intercon_test(); .ADR_I(S3_ADR_I), .DAT_I(S3_DAT_I), .DAT_O(S3_DAT_O), + .SEL_I(S3_SEL_I), .RST_I(RST), .STB_I(S3_STB_I), .WE_I(S3_WE_I), @@ -210,6 +218,11 @@ module intercon_test(); .M1_STALL_I(M1_STALL_I) ); + assign S0_SEL_I = 1; + assign S1_SEL_I = 1; + assign S2_SEL_I = 1; + assign S3_SEL_I = 1; + integer i; initial begin |