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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-07 19:30:24 +0200 |
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| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-07 19:30:24 +0200 |
| commit | 28d8e73f293e11ac3d92c1186fd51d155297d10d (patch) | |
| tree | 6a3a682604f18e1540a45024e66b7451bf57736b /tests/embedded_bram_slave/rom.mem | |
| parent | eb0c405f4122d416cb416b46d514278ea7dcddbf (diff) | |
| download | AGH-engineering-thesis-28d8e73f293e11ac3d92c1186fd51d155297d10d.tar.gz AGH-engineering-thesis-28d8e73f293e11ac3d92c1186fd51d155297d10d.zip | |
add intercon module, that encapsulates slave_dispatcher and master_arbiter and a bench for it (use adapted operations files from master_arbiter test)
Diffstat (limited to 'tests/embedded_bram_slave/rom.mem')
0 files changed, 0 insertions, 0 deletions