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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-12-31 17:59:37 +0100 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-12-31 17:59:37 +0100 |
| commit | 96e4965c09bd41f11162120d6312f2aae7efe7ea (patch) | |
| tree | 4e0a064e4b1bf22b3247bb8c75dc82ec49dc2f8f /models | |
| parent | 68c80359ba0983bc21a18c0270025be9b441c0bb (diff) | |
| download | AGH-engineering-thesis-96e4965c09bd41f11162120d6312f2aae7efe7ea.tar.gz AGH-engineering-thesis-96e4965c09bd41f11162120d6312f2aae7efe7ea.zip | |
Add Wishbone datasheets
Diffstat (limited to 'models')
| -rw-r--r-- | models/master.v | 39 | ||||
| -rw-r--r-- | models/slave.v | 40 |
2 files changed, 78 insertions, 1 deletions
diff --git a/models/master.v b/models/master.v index fbcb197..e23474a 100644 --- a/models/master.v +++ b/models/master.v @@ -4,7 +4,46 @@ * It performs a sequence of wishbone writes, reads and waits based on contents * of provided .mem file. It prints error messages whenever the value it reads * if different from the one it expects. + * +/* + * A Wishbone SLAVE testing module (a "mock") + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | mock MASTER model for test benches | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | parametrizable (WORD_SIZE bytes) | + * | Data port, granularity | parametrizable | + * | | (WORD_SIZE/SEL_LINES bytes) | + * | Data port, maximum operand size | same as data port size | + * | Data transfer ordering | Little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | parametrizable (ADR_BITS bits) | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_I | ACK_I | + * | | ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | SEL_O | SEL_O | + * | | STB_O | STB_O | + * | | CYC_O | CYC_O | + * | | WE_O | WE_O | + * | | RST_I | RST_I | + * | | STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | Should only be used in simulation, | + * | | not synthesizable. | */ + `default_nettype none `include "messages.vh" diff --git a/models/slave.v b/models/slave.v index ed12a73..87c0aa8 100644 --- a/models/slave.v +++ b/models/slave.v @@ -1,4 +1,42 @@ -/* A wishbone slave testing module (a "mock") */ +/* + * A Wishbone SLAVE testing module (a "mock") + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | mock memory model for test benches | + * |---------------------------------+-----------------------------------------| + * | | SLAVE, pipelined READ/WRITE | + * | Supported cycles | (WRITE ability can be disabled | + * | | through module parameter) | + * |---------------------------------+-----------------------------------------| + * | Data port, size | parametrizable (WORD_SIZE bytes) | + * | Data port, granularity | parametrizable | + * | | (WORD_SIZE/SEL_LINES bytes) | + * | Data port, maximum operand size | same as data port size | + * | Data transfer ordering | Little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | parametrizable (ADR_BITS bits) | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | Special requirements | Should only be used in simulation, | + * | | not synthesizable. | + */ + `default_nettype none `include "messages.vh" |