diff options
Diffstat (limited to 'models/slave.v')
| -rw-r--r-- | models/slave.v | 40 |
1 files changed, 39 insertions, 1 deletions
diff --git a/models/slave.v b/models/slave.v index ed12a73..87c0aa8 100644 --- a/models/slave.v +++ b/models/slave.v @@ -1,4 +1,42 @@ -/* A wishbone slave testing module (a "mock") */ +/* + * A Wishbone SLAVE testing module (a "mock") + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | mock memory model for test benches | + * |---------------------------------+-----------------------------------------| + * | | SLAVE, pipelined READ/WRITE | + * | Supported cycles | (WRITE ability can be disabled | + * | | through module parameter) | + * |---------------------------------+-----------------------------------------| + * | Data port, size | parametrizable (WORD_SIZE bytes) | + * | Data port, granularity | parametrizable | + * | | (WORD_SIZE/SEL_LINES bytes) | + * | Data port, maximum operand size | same as data port size | + * | Data transfer ordering | Little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | parametrizable (ADR_BITS bits) | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | Special requirements | Should only be used in simulation, | + * | | not synthesizable. | + */ + `default_nettype none `include "messages.vh" |