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authorWojciech Kosior <kwojtus@protonmail.com>2020-09-08 21:00:13 +0200
committerWojciech Kosior <kwojtus@protonmail.com>2020-09-08 21:00:13 +0200
commitbc43ceac936b48fdccfcac33e172e176273d504f (patch)
treede2723df14a512c214d0fb991a183c363fae042a /include
parentcd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c (diff)
downloadAGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.tar.gz
AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.zip
enable slave and master models to use SEL_ signal
Diffstat (limited to 'include')
-rw-r--r--include/macroasm.vh10
1 files changed, 6 insertions, 4 deletions
diff --git a/include/macroasm.vh b/include/macroasm.vh
index e6a2893..f43c809 100644
--- a/include/macroasm.vh
+++ b/include/macroasm.vh
@@ -22,7 +22,9 @@ operations:
3 - deselect (CYC_O low for one tick)
))
-`define READ(addr, expected_data) 0 addr expected_data
-`define WRITE(addr, data) 1 addr data
-`define WAIT 2 x x
-`define DESELECT 3 x x
+`define READ(addr, expected_data) 0 addr expected_data FFFF
+`define READS(addr, expected_data, mask) 0 addr expected_data mask
+`define WRITE(addr, data) 1 addr data FFFF
+`define WRITES(addr, data, mask) 1 addr data mask
+`define WAIT 2 x x x
+`define DESELECT 3 x x x