cleanup unused registers

1 files changed, 4 insertions, 27 deletions

diff --git a/src/example.v b/src/example.v
index dd1798c..c83bea2 100644
--- a/src/example.v
+++ b/src/example.v
@@ -319,8 +319,6 @@ module vga_timing(input wire       clock_50mhz,
 
 		  output reg 	   h_sync,
 		  output reg 	   v_sync,
-		  output reg [9:0] col,
-		  output reg [8:0] row,
 		  output reg 	   display_on,
 		  output wire 	   pixel_starting,
 		  output wire 	   row_starting);
@@ -365,8 +363,6 @@ module vga_timing(input wire       clock_50mhz,
 
 	 h_sync <= ~h_pol;
 	 v_sync <= ~v_pol;
-	 row <= 0;
-	 col <= 0;
 	 display_on <= 0;
       end // if (reset)
       else begin
@@ -379,25 +375,17 @@ module vga_timing(input wire       clock_50mhz,
 	       h_counter <= h_counter + 1;
 
 	       h_sync <= h_pol ^ (h_counter < h_pulse_start - 1 || h_counter >= h_pulse_end - 1);
-
-	       if (h_counter >= h_active_video_start)
-		 col <= col + 1;
 	    end
 	    else begin
 	       h_counter <= 0;
-	       col <= 0;
 
 	       if (v_counter < v_frame_end - 1) begin
 		  v_counter <= v_counter + 1;
 
 		  v_sync <= v_pol ^ (v_counter < v_pulse_start - 1 || v_counter >= v_pulse_end - 1);
-
-		  if (v_counter >= v_active_video_start)
-		    row <= row + 1;
 	       end
 	       else begin
 		  v_counter <= 0;
-		  row <= 0;
 	       end // else: !if(v_counter < v_frame_end - 1)
 	    end // else: !if(h_counter < h_frame_end - 1)
 	 end // if (divider == 1'b1)
@@ -405,7 +393,7 @@ module vga_timing(input wire       clock_50mhz,
    end // always @ (posedge clock_50mhz)
 
    assign pixel_starting = display_on && divider == 1'b0;
-   assign row_starting = pixel_starting && col == 0;
+   assign row_starting = pixel_starting && h_counter == h_active_video_start;
 endmodule // vga_timing
 
 module vga_pass_colors(input wire       clock_50mhz,
@@ -466,16 +454,14 @@ module vga_hexmode(input wire         clock_50mhz,
 		   output wire [2:0]  vga_green,
 		   output wire [2:0]  vga_blue
 		   );
-   wire [9:0] 			      col_next_tick;
-   wire [8:0] 			      row_next_tick;
    wire 			      h_sync_next_tick;
    wire 			      v_sync_next_tick;
    wire 			      display_on_next_tick;
    wire 			      pixel_starting_next_tick;
    wire 			      row_starting_next_tick;
 
-   vga_timing timing(clock_50mhz, reset, h_sync_next_tick, v_sync_next_tick,
-		     col_next_tick, row_next_tick, display_on_next_tick,
+   vga_timing timing(clock_50mhz, reset,
+		     h_sync_next_tick, v_sync_next_tick, display_on_next_tick,
 		     pixel_starting_next_tick, row_starting_next_tick);
 
    parameter queue_size = 4;
@@ -543,9 +529,6 @@ module vga_hexmode(input wire         clock_50mhz,
    /* If new read can start, the previous one is ignored */
    assign reading = reading_state == 1 && !(want_to_read);
 
-   reg [11:0] 			      word_idx_at_some_point;
-   reg [1:0] 			      digits_in_queue_at_some_point;
-   reg [1:0] 			      reading_state_at_some_point;
    always @ (posedge clock_50mhz) begin
       if (reset) begin
 	 digits_queue <= 16'bxxxxxxxxxxxxxxxx;
@@ -554,15 +537,9 @@ module vga_hexmode(input wire         clock_50mhz,
 	 digit_x <= digit_h_pixels - 1;
 	 digit_y <= digit_v_pixels - 1;
 	 word_in_line <= 0;
-	 word_idx <= 0; word_idx_at_some_point <= 0; digits_in_queue_at_some_point <= 0; reading_state_at_some_point <= 0;
+	 word_idx <= 0;
       end
       else begin
-	 if (pixel_starting_next_tick && col_next_tick == 3 && row_next_tick == 1) begin
-	    word_idx_at_some_point <= word_idx;
-	    digits_in_queue_at_some_point <= digits_in_queue;
-	    reading_state_at_some_point <= reading_state;
-	 end
-
 	 if (pixel_starting_next_tick)
 	   digit_x <= subsequent_digit_x;