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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-04-01 11:49:22 +0200 |
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| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-04-01 11:49:22 +0200 |
| commit | 3cdcd0cbaf54520b8e9111048b8729cc973ded28 (patch) | |
| tree | 03cfe7d01974408b00dc5e5d190f07dffaf39acf | |
| download | AGH-engineering-thesis-3cdcd0cbaf54520b8e9111048b8729cc973ded28.tar.gz AGH-engineering-thesis-3cdcd0cbaf54520b8e9111048b8729cc973ded28.zip | |
add simple readme
| -rw-r--r-- | README.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/README.txt b/README.txt new file mode 100644 index 0000000..976a54a --- /dev/null +++ b/README.txt @@ -0,0 +1,2 @@ +This repository shall contain the the code for 'Laboratory station based on programmable logic device for WebAssembly execution evaluation' developed as my engineering thesis at AGH University of Science and Technology in Cracov, Poland. +The project is going to utilize the Verilog HDL. Icarus Verilog Simulator shall be used for simulation and test benches, while Yosys, arachne-pnr/nextpnr and icestorm are the tools chosen for synthesis, p&r and bitstream generation for Olimex's iCE40HX8K-EVB FPGA. |