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authorvetch <vetch97@gmail.com>2020-01-18 19:13:17 +0100
committervetch <vetch97@gmail.com>2020-01-18 19:13:17 +0100
commitf540834c09905f848139371005d077577eabdd57 (patch)
tree7420a43e63be72a0c860f325ea65aed603aee65f /src/arm/PL1/kernel/interrupt_vector.S
parentdfd6177fea6769a0e7dcd2d2205e5a795bba3553 (diff)
parentf5c83b679ced1d1900613e049c31ad56cf903c1e (diff)
downloadrpi-MMU-example-f540834c09905f848139371005d077577eabdd57.tar.gz
rpi-MMU-example-f540834c09905f848139371005d077577eabdd57.zip
Merge branch 'bob' of https://repo.or.cz/RPi-MMU-example into alice
Diffstat (limited to 'src/arm/PL1/kernel/interrupt_vector.S')
-rw-r--r--src/arm/PL1/kernel/interrupt_vector.S5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arm/PL1/kernel/interrupt_vector.S b/src/arm/PL1/kernel/interrupt_vector.S
index 1ec80f7..3afc193 100644
--- a/src/arm/PL1/kernel/interrupt_vector.S
+++ b/src/arm/PL1/kernel/interrupt_vector.S
@@ -8,9 +8,12 @@ _interrupt_vectors:
b irq_handler_caller
b fiq_handler_caller
+// from what I've heard, reset is never used on the Pi;
+// in our case it should run once - when stage1 of the kernel
+// jumps to stage2
reset_handler_caller:
ldr sp, =_supervisor_stack_top
- ldr r5, =reset_handler
+ ldr r5, =setup
bx r5
undef_handler_caller: