change wording so as not to suggest msr and mrs cannot be used at all in PL0 (they can - for accessing APSR)

1 files changed, 1 insertions, 1 deletions

diff --git a/processor-modes-explained.txt b/processor-modes-explained.txt
index 5690291..d6f04c3 100644
--- a/processor-modes-explained.txt
+++ b/processor-modes-explained.txt
@@ -15,7 +15,7 @@ Processor can operate in one of 2 privilege levels (although, again, extensions
  · PL0 - privilege level 0
  · PL1 - privilege level 1
 
-Processor modes have their assigned privilege levels. User mode has privilege level 0 and all other modes have privilege level 1. Code executing in one of privileged modes is allowed to do more things, than user mode code, i.e. writing and reading some of the coprocessor registers, executing some privileged instructions (i.e. mrs and msr, that allow operation on CPSR, as well as other modes' registers), accessing privileged memory and changing the mode (without causing an interrupt). Attempts to perform those actions in user mode result either in undefined (within some limits) behaviour or an exception (depending on what action is considered).
+Processor modes have their assigned privilege levels. User mode has privilege level 0 and all other modes have privilege level 1. Code executing in one of privileged modes is allowed to do more things, than user mode code, i.e. writing and reading some of the coprocessor registers, executing some privileged instructions (i.e. mrs and msr, when used to reference CPSR, as well as other modes' registers), accessing privileged memory and changing the mode (without causing an interrupt). Attempts to perform those actions in user mode result either in undefined (within some limits) behaviour or an exception (depending on what action is considered).
 
 User mode is the one, in which application programs usually run. Other modes are usually used by the operating system's kernel. Lack of privileges in user mode allows PL1 code to control execution of PL0 code.