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| author | Wojtek Kosior <kwojtus@protonmail.com> | 2020-01-18 07:41:35 +0100 |
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| committer | Wojtek Kosior <kwojtus@protonmail.com> | 2020-01-18 07:41:35 +0100 |
| commit | 2b346bc786ebec5f6c0edc4c7e688de455203dc1 (patch) | |
| tree | 852e26d84f740d82801f1ee3355d0c3cd970fb7d | |
| parent | 9698e82369db966b12b5a0a0fa52515b2ffe41d0 (diff) | |
| download | rpi-MMU-example-2b346bc786ebec5f6c0edc4c7e688de455203dc1.tar.gz rpi-MMU-example-2b346bc786ebec5f6c0edc4c7e688de455203dc1.zip | |
start explaining Program Status Registers
| -rw-r--r-- | PSRs-explained.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/PSRs-explained.txt b/PSRs-explained.txt new file mode 100644 index 0000000..de5c0fb --- /dev/null +++ b/PSRs-explained.txt @@ -0,0 +1,3 @@ +CPSR (Current Program Status Register) is a register, bits of which contain and/or determine various aspects of execution, i.e. condition flags, execution state (arm, thumb or jazelle), endianness state, execution mode <link to doc explaining modes> and interrupt mask. This register is readable and writeable with the use of mrs and msr instructions from any PL1 mode, thus it is possible to change things like mode or interrupt mask by writing to this register. +Additionally, there are other registers with the same or simillar bit fields as CPSR. Those PSRs (Program Status Registers) are: +ยท APSR (Application Program Status Register) |