1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
`include "macroasm.vh" // look into macroasm.vh for more info
// Those are the operations performed by
// master 0 (the one prioritized by arbiter)
`WRITE(00000, abcd)
`WAIT
`READ (00000, abcd)
`WRITE(50001, 1234)
`READ (00000, abcd)
`DESELECT
`DESELECT
`READ (50001, 1234)
`WRITE(a1010, a2a2)
`WRITE(50001, 4321)
`READ (a1010, a2a2)
`WAIT
`WAIT
`WAIT
`WAIT
`WAIT
// Only values written until this point will also be checked by master 1
`DESELECT
`DESELECT
`DESELECT
`WAIT
`DESELECT
// Let's force some interleaved single operations by both masters
`WRITE(f041c, 8a9b)
`DESELECT
`WRITE(b043e, acbd)
`DESELECT
`READ (b043e, acbd)
`DESELECT
`READ (f041c, 8a9b)
`DESELECT
`WRITE(70450, cedf)
`DESELECT
`WRITE(00472, e0f1)
`DESELECT
`READ (00472, e0f1)
`DESELECT
`READ (70450, cedf)
`DESELECT
`WAIT
`READ (50001, 4321)
// The other master should write the values we check below during its first few
// blocks of operations. Although we have no means of synchronizing masters, we
// assume, that when 1 of them does a `DESELECT, other one can take over the
// bus. Because we do have `DESELECTs above, we can expect at least the first
// sets of other master's operations to have completed once we get here.
`READ (30000, 03e8)
`READ (50005, 0403)
`READ (50120, 0120)
`READ (b0005, 22ef)
`READ (0001a, 0a1b)
|
