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`default_nettype none
module vga_example(input wire clock_100mhz,
input wire reset,
output reg h_sync,
output reg v_sync,
output reg [2:0] vga_red,
output reg [2:0] vga_green,
output reg [2:0] vga_blue
);
wire [9:0] col_next_tick;
wire [8:0] row_next_tick;
wire h_sync_next_tick;
wire v_sync_next_tick;
wire display_on_next_tick;
vga vga(clock_100mhz, ~reset, h_sync_next_tick, v_sync_next_tick,
col_next_tick, row_next_tick, display_on_next_tick);
always @ (posedge clock_100mhz) begin
h_sync <= h_sync_next_tick;
v_sync <= v_sync_next_tick;
if (display_on_next_tick) begin
vga_red <= 3'b000;
vga_green <= row_next_tick < 220 ? 3'b111 : 3'b000;
vga_blue <= row_next_tick >= 220 ? 3'b111 : 3'b000;
end
else begin
vga_red <= 0;
vga_green <= 0;
vga_blue <= 0;
end
end // always @ (posedge clock_100mhz)
endmodule // vga_example
module vga(input wire clock_100mhz,
input wire reset,
output reg h_sync,
output reg v_sync,
output reg [9:0] col,
output reg [8:0] row,
output reg display_on);
parameter h_pixels = 640;
parameter v_pixels = 480;
parameter h_front_porch = 16;
parameter v_front_porch = 10;
parameter h_pulse = 96;
parameter v_pulse = 2;
parameter h_back_porch = 48;
parameter v_back_porch = 33;
parameter h_pol = 1'b0;
parameter v_pol = 1'b1;
parameter h_pulse_start = h_front_porch;
parameter v_pulse_start = v_front_porch;
parameter h_pulse_end = h_front_porch + h_pulse;
parameter v_pulse_end = v_front_porch + v_pulse;
parameter h_active_video_start = h_front_porch + h_pulse + h_back_porch;
parameter v_active_video_start = v_front_porch + v_pulse + v_back_porch;
parameter h_frame_end = h_active_video_start + h_pixels;
parameter v_frame_end = v_active_video_start + v_pixels;
reg [9:0] h_counter;
reg [9:0] v_counter;
reg [1:0] divider; // 25MHz
always @ (posedge clock_100mhz) begin
if (reset) begin
divider <= 2'b00;
h_counter <= 0;
v_counter <= 0;
h_sync <= ~h_pol;
v_sync <= ~v_pol;
row <= 0;
col <= 0;
display_on <= 0;
end // if (reset)
else begin
divider <= divider + 1;
if (divider == 2'b11) begin
display_on <= (h_counter < h_frame_end - 1) &&
(h_counter >= h_active_video_start - 1) &&
(v_counter < v_frame_end) &&
(v_counter >= v_active_video_start);
if (h_counter < h_frame_end - 1) begin
h_counter <= h_counter + 1;
h_sync <= h_pol ^ (h_counter < h_pulse_start - 1 || h_counter >= h_pulse_end - 1);
if (h_counter >= h_active_video_start)
col <= col + 1;
end
else begin
h_counter <= 0;
col <= 0;
if (v_counter < v_frame_end - 1) begin
v_counter <= v_counter + 1;
v_sync <= v_pol ^ (v_counter < v_pulse_start - 1 || v_counter >= v_pulse_end - 1);
if (v_counter >= v_active_video_start)
row <= row + 1;
end
else begin
v_counter <= 0;
row <= 0;
end // else: !if(v_counter < v_frame_end - 1)
end // else: !if(h_counter < h_frame_end - 1)
end // if (divider == 2'b11)
end // else: !if(reset)
end // always @ (posedge clock_100mhz)
endmodule // vga
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