1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
|
/* All this module does is combining slave_dispatcher with master_arbiter */
`default_nettype none
module intercon
(
input wire CLK,
input wire RST,
input wire S0_ACK_O,
output wire [17:0] S0_ADR_I,
output wire [15:0] S0_DAT_I,
input wire [15:0] S0_DAT_O,
output wire S0_STB_I,
output wire S0_WE_I,
input wire S0_STALL_O,
input wire S1_ACK_O,
output wire [17:0] S1_ADR_I,
output wire [15:0] S1_DAT_I,
input wire [15:0] S1_DAT_O,
output wire S1_STB_I,
output wire S1_WE_I,
input wire S1_STALL_O,
input wire S2_ACK_O,
output wire [16:0] S2_ADR_I,
output wire [15:0] S2_DAT_I,
input wire [15:0] S2_DAT_O,
output wire S2_STB_I,
output wire S2_WE_I,
input wire S2_STALL_O,
input wire S3_ACK_O,
output wire [16:0] S3_ADR_I,
output wire [15:0] S3_DAT_I,
input wire [15:0] S3_DAT_O,
output wire S3_STB_I,
output wire S3_WE_I,
input wire S3_STALL_O,
input wire S4_ACK_O,
output wire [16:0] S4_ADR_I,
output wire [15:0] S4_DAT_I,
input wire [15:0] S4_DAT_O,
output wire S4_STB_I,
output wire S4_WE_I,
input wire S4_STALL_O,
input wire S5_ACK_O,
output wire [16:0] S5_ADR_I,
output wire [15:0] S5_DAT_I,
input wire [15:0] S5_DAT_O,
output wire S5_STB_I,
output wire S5_WE_I,
input wire S5_STALL_O,
output wire M0_ACK_I,
input wire [19:0] M0_ADR_O,
output wire [15:0] M0_DAT_I,
input wire [15:0] M0_DAT_O,
input wire M0_STB_O,
input wire M0_CYC_O,
input wire M0_WE_O,
output wire M0_STALL_I,
output wire M1_ACK_I,
input wire [19:0] M1_ADR_O,
output wire [15:0] M1_DAT_I,
input wire [15:0] M1_DAT_O,
input wire M1_STB_O,
input wire M1_CYC_O,
input wire M1_WE_O,
output wire M1_STALL_I
);
wire S_COMBINED_ACK_O;
wire [19:0] S_COMBINED_ADR_I;
wire [15:0] S_COMBINED_DAT_I;
wire [15:0] S_COMBINED_DAT_O;
wire S_COMBINED_STB_I;
wire S_COMBINED_WE_I;
wire S_COMBINED_STALL_O;
wire M_COMBINED_ACK_I;
wire [19:0] M_COMBINED_ADR_O;
wire [15:0] M_COMBINED_DAT_I;
wire [15:0] M_COMBINED_DAT_O;
wire M_COMBINED_STB_O;
wire M_COMBINED_CYC_O;
wire M_COMBINED_WE_O;
wire M_COMBINED_STALL_I;
slave_dispatcher dispatcher
(
.CLK(CLK),
.RST(RST),
.S0_ACK_O(S0_ACK_O),
.S0_ADR_I(S0_ADR_I),
.S0_DAT_I(S0_DAT_I),
.S0_DAT_O(S0_DAT_O),
.S0_STB_I(S0_STB_I),
.S0_WE_I(S0_WE_I),
.S0_STALL_O(S0_STALL_O),
.S1_ACK_O(S1_ACK_O),
.S1_ADR_I(S1_ADR_I),
.S1_DAT_I(S1_DAT_I),
.S1_DAT_O(S1_DAT_O),
.S1_STB_I(S1_STB_I),
.S1_WE_I(S1_WE_I),
.S1_STALL_O(S1_STALL_O),
.S2_ACK_O(S2_ACK_O),
.S2_ADR_I(S2_ADR_I),
.S2_DAT_I(S2_DAT_I),
.S2_DAT_O(S2_DAT_O),
.S2_STB_I(S2_STB_I),
.S2_WE_I(S2_WE_I),
.S2_STALL_O(S2_STALL_O),
.S3_ACK_O(S3_ACK_O),
.S3_ADR_I(S3_ADR_I),
.S3_DAT_I(S3_DAT_I),
.S3_DAT_O(S3_DAT_O),
.S3_STB_I(S3_STB_I),
.S3_WE_I(S3_WE_I),
.S3_STALL_O(S3_STALL_O),
.S4_ACK_O(S4_ACK_O),
.S4_ADR_I(S4_ADR_I),
.S4_DAT_I(S4_DAT_I),
.S4_DAT_O(S4_DAT_O),
.S4_STB_I(S4_STB_I),
.S4_WE_I(S4_WE_I),
.S4_STALL_O(S4_STALL_O),
.S5_ACK_O(S5_ACK_O),
.S5_ADR_I(S5_ADR_I),
.S5_DAT_I(S5_DAT_I),
.S5_DAT_O(S5_DAT_O),
.S5_STB_I(S5_STB_I),
.S5_WE_I(S5_WE_I),
.S5_STALL_O(S5_STALL_O),
.S_COMBINED_ACK_O(S_COMBINED_ACK_O),
.S_COMBINED_ADR_I(S_COMBINED_ADR_I),
.S_COMBINED_DAT_I(S_COMBINED_DAT_I),
.S_COMBINED_DAT_O(S_COMBINED_DAT_O),
.S_COMBINED_STB_I(S_COMBINED_STB_I),
.S_COMBINED_WE_I(S_COMBINED_WE_I),
.S_COMBINED_STALL_O(S_COMBINED_STALL_O)
);
master_arbiter arbiter
(
.CLK(CLK),
.RST(RST),
.M0_ACK_I(M0_ACK_I),
.M0_ADR_O(M0_ADR_O),
.M0_DAT_I(M0_DAT_I),
.M0_DAT_O(M0_DAT_O),
.M0_STB_O(M0_STB_O),
.M0_CYC_O(M0_CYC_O),
.M0_WE_O(M0_WE_O),
.M0_STALL_I(M0_STALL_I),
.M1_ACK_I(M1_ACK_I),
.M1_ADR_O(M1_ADR_O),
.M1_DAT_I(M1_DAT_I),
.M1_DAT_O(M1_DAT_O),
.M1_STB_O(M1_STB_O),
.M1_CYC_O(M1_CYC_O),
.M1_WE_O(M1_WE_O),
.M1_STALL_I(M1_STALL_I),
.M_COMBINED_ACK_I(M_COMBINED_ACK_I),
.M_COMBINED_ADR_O(M_COMBINED_ADR_O),
.M_COMBINED_DAT_I(M_COMBINED_DAT_I),
.M_COMBINED_DAT_O(M_COMBINED_DAT_O),
.M_COMBINED_STB_O(M_COMBINED_STB_O),
.M_COMBINED_CYC_O(M_COMBINED_CYC_O),
.M_COMBINED_WE_O(M_COMBINED_WE_O),
.M_COMBINED_STALL_I(M_COMBINED_STALL_I)
);
assign M_COMBINED_ACK_I = S_COMBINED_ACK_O;
assign M_COMBINED_DAT_I = S_COMBINED_DAT_O;
assign M_COMBINED_STALL_I = S_COMBINED_STALL_O;
assign S_COMBINED_ADR_I = M_COMBINED_ADR_O;
assign S_COMBINED_DAT_I = M_COMBINED_DAT_O;
assign S_COMBINED_STB_I = M_COMBINED_STB_O && M_COMBINED_CYC_O;
assign S_COMBINED_WE_I = M_COMBINED_WE_O;
endmodule // intercon
|
