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|
PROJ_DIR := .
include Makefile.config
include Makefile.util
include tools/Makefile.tools
TEST_TARGETS := $(addprefix test_,$(shell ls tests))
TOOLS_TARGETS := $(addprefix tools/,$(TOOLS))
GENERATED_MEM_FILES := $(shell find design/ -name "*.s.tcl")
GENERATED_MEM_FILES := $(basename $(basename $(GENERATED_MEM_FILES)))
GENERATED_MEM_FILES := $(addsuffix .mem,$(GENERATED_MEM_FILES))
all : design.bin
design.v : design/rom.mem design/*.v
$(IV) -Iinclude/ -E $(filter %.v,$^) \
-DROM_WORDS_COUNT=$(call FILE_LINES,$<) -o $@
design.json : design.v design/rom.mem design/font.mem
$(YOSYS) -p 'read_verilog -defer $<' \
-p 'synth_ice40 -top $(TOPMODULE) -json $@'
design.asc : design.json $(PCF)
$(PNR) --hx8k --asc $@ --pcf $(PCF) --json $< --package ct256
design.bin : design.asc
$(ICEPACK) $< $@
timing.rpt : design.asc
$(ICETIME) -d hx8k -mtr $@ $<
prog : design.bin
sudo iceprogduino $<
CALL_TESTS = \
cd tests/; \
for TEST in $(1); do \
echo "** $$TEST "; \
if ! $(MAKE) -C $$TEST $(2) 3>&1 1>/dev/null 2>&3; then \
FAIL=true; \
fi; \
done; \
[ "$$FAIL" != true ]
test :
$(call CALL_TESTS,*)
# Will skip VGA tests, because they take loooong time
quicktest :
$(call CALL_TESTS,*,QUICK_TEST=1)
stack_machine_test :
$(call CALL_TESTS,stack_machine_*)
stack_machine_quicktest :
$(call CALL_TESTS,stack_machine_*,QUICK_TEST=1)
wasm_compile_test :
$(call CALL_TESTS,wasm_compile_*)
$(TEST_TARGETS) : test_% :
$(MAKE) -C tests/$*
tools : $(TOOLS_TARGETS)
$(TOOLS_TARGETS) : tools/% :
$(MAKE) -C tools/ $*
clean :
for TEST in tests/*; do $(MAKE) -C $$TEST clean >/dev/null; done
rm $(GENERATED_MEM_FILES) 2>/dev/null || true
$(MAKE) -C tools/ clean >/dev/null
rm $(addprefix design.,v json asc bin) timing.rpt 2>/dev/null || true
.PHONY : all tools test quicktest stack_machine_test stack_machine_quicktest \
wasm_compile_test $(TEST_TARGETS) $(TOOLS_TARGETS) tools
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