| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-09-08 | enable slave and master models to use SEL_ signal | Wojciech Kosior |
| 2020-09-07 | add intercon module, that encapsulates slave_dispatcher and master_arbiter an... | Wojciech Kosior |
| 2020-09-07 | rename intercon to slave_dispatcher (soc module will remporarily stop working... | Wojciech Kosior |
| 2020-09-01 | start anew | Wojciech Kosior |
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index : AGH-engineering-thesis | |
| Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland |
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