| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-11-21 | increase number of wb slaves, that can be attached to the intercon | Wojciech Kosior |
| 2020-11-03 | incorporate SPI module into main design | Wojciech Kosior |
| 2020-09-07 | update soc toplevel module to use new version of stack machine | Wojciech Kosior |
| 2020-09-02 | add topmost module of the synthesizable design | Wojciech Kosior |
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index : AGH-engineering-thesis | |
| Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland |
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