| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-09-07 | add intercon module, that encapsulates slave_dispatcher and master_arbiter ↵ | Wojciech Kosior | |
| and a bench for it (use adapted operations files from master_arbiter test) | |||
| 2020-09-07 | rename intercon to slave_dispatcher (soc module will remporarily stop ↵ | Wojciech Kosior | |
| working from this commit on) | |||
| 2020-09-01 | start anew | Wojciech Kosior | |
 |
index : AGH-engineering-thesis | |
| Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland |
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