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-rw-r--r--tests/master_arbiter/operations0.memv55
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diff --git a/tests/master_arbiter/operations0.memv b/tests/master_arbiter/operations0.memv
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+`include "macroasm.vh" // look into macroasm.vh for more info
+
+// Those are the operations performed by
+// master 0 (the one prioritized by arbiter)
+`WRITE(00000, abcd)
+`WAIT
+`READ (00000, abcd)
+`WRITE(00001, 1234)
+`READ (00000, abcd)
+`DESELECT
+`DESELECT
+`READ (00001, 1234)
+`WRITE(01010, a2a2)
+`WRITE(00001, 4321)
+`READ (01010, a2a2)
+`WAIT
+`WAIT
+`WAIT
+`WAIT
+`WAIT
+// Only values written until this point will also be checked by master 1
+`DESELECT
+`DESELECT
+`DESELECT
+`WAIT
+`DESELECT
+// Let's force some interleaved single operations by both masters
+`WRITE(0001c, 8a9b)
+`DESELECT
+`WRITE(0003e, acbd)
+`DESELECT
+`READ (0003e, acbd)
+`DESELECT
+`READ (0001c, 8a9b)
+`DESELECT
+`WRITE(00050, cedf)
+`DESELECT
+`WRITE(00072, e0f1)
+`DESELECT
+`READ (00072, e0f1)
+`DESELECT
+`READ (00050, cedf)
+`DESELECT
+`WAIT
+`READ (00001, 4321)
+// The other master should write the values we check below during its first few
+// blocks of operations. Although we have no means of synchronizing masters, we
+// assume, that when 1 of them does a `DESELECT, other one can take over the
+// bus. Because we do have `DESELECTs above, we can expect at least the first
+// sets of other master's operations to have completed once we get here.
+`READ (30000, 03e8)
+`READ (30005, 0403)
+`READ (30120, 0120)
+`READ (b0005, 22ef)
+`READ (3001a, 0a1b)