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Diffstat (limited to 'models/master.v')
| -rw-r--r-- | models/master.v | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/models/master.v b/models/master.v index fbcb197..e23474a 100644 --- a/models/master.v +++ b/models/master.v @@ -4,7 +4,46 @@ * It performs a sequence of wishbone writes, reads and waits based on contents * of provided .mem file. It prints error messages whenever the value it reads * if different from the one it expects. + * +/* + * A Wishbone SLAVE testing module (a "mock") + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | mock MASTER model for test benches | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | parametrizable (WORD_SIZE bytes) | + * | Data port, granularity | parametrizable | + * | | (WORD_SIZE/SEL_LINES bytes) | + * | Data port, maximum operand size | same as data port size | + * | Data transfer ordering | Little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | parametrizable (ADR_BITS bits) | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_I | ACK_I | + * | | ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | SEL_O | SEL_O | + * | | STB_O | STB_O | + * | | CYC_O | CYC_O | + * | | WE_O | WE_O | + * | | RST_I | RST_I | + * | | STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | Should only be used in simulation, | + * | | not synthesizable. | */ + `default_nettype none `include "messages.vh" |