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-rw-r--r--design/slave_dispatcher.v (renamed from design/intercon.v)90
1 files changed, 33 insertions, 57 deletions
diff --git a/design/intercon.v b/design/slave_dispatcher.v
index bf908af..8cd0022 100644
--- a/design/intercon.v
+++ b/design/slave_dispatcher.v
@@ -1,60 +1,49 @@
`default_nettype none
-module intercon
+module slave_dispatcher
(
input wire CLK,
input wire RST,
input wire S0_ACK_O,
- output wire S0_CLK_I,
output wire [17:0] S0_ADR_I,
output wire [15:0] S0_DAT_I,
input wire [15:0] S0_DAT_O,
- output wire S0_RST_I,
output wire S0_STB_I,
output wire S0_WE_I,
input wire S0_STALL_O,
input wire S1_ACK_O,
- output wire S1_CLK_I,
output wire [17:0] S1_ADR_I,
output wire [15:0] S1_DAT_I,
input wire [15:0] S1_DAT_O,
- output wire S1_RST_I,
output wire S1_STB_I,
output wire S1_WE_I,
input wire S1_STALL_O,
input wire S2_ACK_O,
- output wire S2_CLK_I,
output wire [17:0] S2_ADR_I,
output wire [15:0] S2_DAT_I,
input wire [15:0] S2_DAT_O,
- output wire S2_RST_I,
output wire S2_STB_I,
output wire S2_WE_I,
input wire S2_STALL_O,
input wire S3_ACK_O,
- output wire S3_CLK_I,
output wire [17:0] S3_ADR_I,
output wire [15:0] S3_DAT_I,
input wire [15:0] S3_DAT_O,
- output wire S3_RST_I,
output wire S3_STB_I,
output wire S3_WE_I,
input wire S3_STALL_O,
- output wire M_ACK_I,
- output wire M_CLK_I,
- input wire [19:0] M_ADR_O,
- input wire [15:0] M_DAT_O,
- output wire [15:0] M_DAT_I,
- output wire M_RST_I,
- input wire M_STB_O,
- input wire M_CYC_O,
- input wire M_WE_O,
- output wire M_STALL_I
+ output wire S_COMBINED_ACK_O,
+ input wire [19:0] S_COMBINED_ADR_I,
+ input wire [15:0] S_COMBINED_DAT_O,
+ output wire [15:0] S_COMBINED_DAT_I,
+ input wire S_COMBINED_STB_I,
+ input wire S_COMBINED_WE_I,
+ output wire S_COMBINED_STALL_O
);
wire [0:3] acks;
@@ -70,22 +59,21 @@ module intercon
reg [1:0] commands_awaiting;
reg [1:0] slave_last_accessed;
- wire operation_requested;
wire working;
wire [1:0] slave_accessed;
- wire slave_switch;
+ wire slave_switch;
wire [1:0] commands_awaiting_next_tick;
- assign operation_requested = M_STB_O && M_CYC_O;
- assign working = commands_awaiting || operation_requested;
+ assign working = commands_awaiting || S_COMBINED_STB_I;
assign slave_accessed = commands_awaiting ? slave_last_accessed :
- M_ADR_O[19:18];
- assign M_ACK_I = acks[slave_accessed] && working;
- assign M_DAT_I = datas[slave_accessed];
- assign slave_switch = slave_accessed != M_ADR_O[19:18];
- assign M_STALL_I = stalls[slave_accessed] || slave_switch ||
- (commands_awaiting == 3 && !M_ACK_I);
+ S_COMBINED_ADR_I[19:18];
+ assign S_COMBINED_ACK_O = acks[slave_accessed] && working;
+ assign S_COMBINED_DAT_O = datas[slave_accessed];
+ assign slave_switch = slave_accessed != S_COMBINED_ADR_I[19:18];
+ assign S_COMBINED_STALL_O = stalls[slave_accessed] || slave_switch ||
+ (commands_awaiting == 3 && !S_COMBINED_ACK_O);
assign commands_awaiting_next_tick
- = commands_awaiting - M_ACK_I + (operation_requested && !M_STALL_I);
+ = commands_awaiting - S_COMBINED_ACK_O +
+ (S_COMBINED_STB_I && !S_COMBINED_STALL_O);
`ifdef SIMULATION
/* anything could be latched here, this is just to avoid undefined values */
@@ -104,39 +92,27 @@ module intercon
commands_awaiting <= commands_awaiting_next_tick;
end
- assign S0_CLK_I = CLK;
- assign S1_CLK_I = CLK;
- assign S2_CLK_I = CLK;
- assign S3_CLK_I = CLK;
- assign M_CLK_I = CLK;
+ assign S0_ADR_I = S_COMBINED_ADR_I[17:0];
+ assign S1_ADR_I = S_COMBINED_ADR_I[17:0];
+ assign S2_ADR_I = S_COMBINED_ADR_I[17:0];
+ assign S3_ADR_I = S_COMBINED_ADR_I[17:0];
- assign S0_RST_I = RST;
- assign S1_RST_I = RST;
- assign S2_RST_I = RST;
- assign S3_RST_I = RST;
- assign M_RST_I = RST;
-
- assign S0_ADR_I = M_ADR_O[17:0];
- assign S1_ADR_I = M_ADR_O[17:0];
- assign S2_ADR_I = M_ADR_O[17:0];
- assign S3_ADR_I = M_ADR_O[17:0];
-
- assign S0_DAT_I = M_DAT_O;
- assign S1_DAT_I = M_DAT_O;
- assign S2_DAT_I = M_DAT_O;
- assign S3_DAT_I = M_DAT_O;
+ assign S0_DAT_I = S_COMBINED_DAT_I;
+ assign S1_DAT_I = S_COMBINED_DAT_I;
+ assign S2_DAT_I = S_COMBINED_DAT_I;
+ assign S3_DAT_I = S_COMBINED_DAT_I;
wire pass_strobe;
- assign pass_strobe = operation_requested && !slave_switch &&
- (commands_awaiting != 3 || M_ACK_I);
+ assign pass_strobe = S_COMBINED_STB_I && !slave_switch &&
+ (commands_awaiting != 3 || S_COMBINED_ACK_O);
assign S0_STB_I = slave_accessed == 0 && pass_strobe;
assign S1_STB_I = slave_accessed == 1 && pass_strobe;
assign S2_STB_I = slave_accessed == 2 && pass_strobe;
assign S3_STB_I = slave_accessed == 3 && pass_strobe;
- assign S0_WE_I = M_WE_O;
- assign S1_WE_I = M_WE_O;
- assign S2_WE_I = M_WE_O;
- assign S3_WE_I = M_WE_O;
-endmodule // intercon
+ assign S0_WE_I = S_COMBINED_WE_I;
+ assign S1_WE_I = S_COMBINED_WE_I;
+ assign S2_WE_I = S_COMBINED_WE_I;
+ assign S3_WE_I = S_COMBINED_WE_I;
+endmodule // slave_dispatcher