diff options
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | design/interface_wrapper.v | 125 | ||||
| -rw-r--r-- | tests/interface_wrapper/operations.memv | 51 | ||||
| -rw-r--r-- | tests/interface_wrapper/test.v | 160 |
4 files changed, 344 insertions, 0 deletions
@@ -55,6 +55,7 @@ TESTS := \ sram_slave \ embedded_bram_slave \ soc_simple_display \ + interface_wrapper \ $(addprefix stack_machine_old_,$(STACK_MACHINE_OLD_TESTS)) \ $(addprefix stack_machine_,$(STACK_MACHINE_TESTS)) @@ -152,6 +153,13 @@ tests/intercon/test.vvp : tests/intercon/operations.mem tests/intercon/test.v \ -DMASTER_OPERATIONS_COUNT=$(call FILE_LINES,$<) \ $(filter %.v,$^) -o $@ +tests/interface_wrapper/test.vvp : tests/interface_wrapper/operations.mem \ + tests/interface_wrapper/test.v models/slave.v models/master.v \ + design/interface_wrapper.v include/messages.vh + $(IV) $(IVFLAGS) -s interface_wrapper_test \ + -DMASTER_OPERATIONS_COUNT=$(call FILE_LINES,$<) \ + $(filter %.v,$^) -o $@ + tests/embedded_bram_slave/test.vvp : tests/embedded_bram_slave/operations.mem \ tests/embedded_bram_slave/rom.mem \ tests/embedded_bram_slave/test.v models/master.v \ diff --git a/design/interface_wrapper.v b/design/interface_wrapper.v new file mode 100644 index 0000000..30d2e49 --- /dev/null +++ b/design/interface_wrapper.v @@ -0,0 +1,125 @@ +/* + * For now, this wrapper ignores SEL_O signals - we'll update it for + * byte-granular accesses later. + */ +`default_nettype none + +module interface_wrapper + ( + input wire CLK_I, + input wire RST_I, + + output wire RAW_ACK_I, + output wire RAW_ERR_I, /* We'll start using it soon */ + input wire [20:0] RAW_ADR_O, + output wire [31:0] RAW_DAT_I, + input wire [31:0] RAW_DAT_O, + input wire [3:0] RAW_SEL_O, /* We'll start using it soon */ + input wire RAW_STB_O, + input wire RAW_CYC_O, + input wire RAW_WE_O, + output wire RAW_STALL_I, + + input wire WRAPPED_ACK_I, + output wire [19:0] WRAPPED_ADR_O, + input wire [15:0] WRAPPED_DAT_I, + output wire [15:0] WRAPPED_DAT_O, + output wire WRAPPED_STB_O, + output wire WRAPPED_CYC_O, + output wire WRAPPED_WE_O, + input wire WRAPPED_STALL_I + ); + + /* RAW -> WRAPPED */ + wire wrapped_request_happens; + assign wrapped_request_happens = WRAPPED_STB_O && !WRAPPED_STALL_I; + + wire raw_request_wanted; + assign raw_request_wanted = RAW_STB_O && RAW_CYC_O; + + reg [19:0] ADR_O_waiting; + reg [31:0] DAT_O_waiting; + reg WE_O_waiting; + reg [1:0] request_out_waiting; + + wire can_accept_request; + assign can_accept_request = !request_out_waiting[0] || + (!request_out_waiting[1] && + wrapped_request_happens); + + assign WRAPPED_ADR_O = request_out_waiting[0] ? + ADR_O_waiting : RAW_ADR_O >> 1; + assign WRAPPED_DAT_O = request_out_waiting[0] ? + DAT_O_waiting[15:0] : RAW_DAT_O[15:0]; + assign WRAPPED_WE_O = request_out_waiting[0] ? + WE_O_waiting : RAW_WE_O; + assign WRAPPED_STB_O = request_out_waiting[0] || raw_request_wanted; + + assign WRAPPED_CYC_O = RAW_CYC_O; + + always @ (posedge CLK_I) begin + if (RST_I) begin + ADR_O_waiting <= 20'bx; + DAT_O_waiting <= 32'bx; + WE_O_waiting <= 1'bx; + request_out_waiting <= 2'b0; + end else begin + if (wrapped_request_happens) begin + if (request_out_waiting[1]) begin + ADR_O_waiting <= ADR_O_waiting + 1; + DAT_O_waiting <= {16'bx, DAT_O_waiting[31:16]}; + request_out_waiting <= {1'b0, request_out_waiting[1]}; + end else begin + ADR_O_waiting <= RAW_ADR_O >> 1; + WE_O_waiting <= RAW_WE_O; + request_out_waiting[0] <= raw_request_wanted; + + if (request_out_waiting[0]) begin + ADR_O_waiting <= RAW_ADR_O >> 1; + DAT_O_waiting <= RAW_DAT_O; + request_out_waiting[1] <= raw_request_wanted; + end else begin + ADR_O_waiting <= (RAW_ADR_O >> 1) + 1; + DAT_O_waiting <= {16'bx, RAW_DAT_O[31:16]}; + request_out_waiting[1] <= 0; + end + end // else: !if(request_out_waiting[1]) + end else if (!request_out_waiting[0]) begin // if (wr_request_happens) + ADR_O_waiting <= RAW_ADR_O >> 1; + WE_O_waiting <= RAW_WE_O; + DAT_O_waiting <= RAW_DAT_O; + request_out_waiting <= {2{raw_request_wanted}}; + end + end // else: !if(RST_I) + end // always @ (posedge CLK_I) + + /* WRAPPED -> RAW */ + wire wrapped_request_completes; + assign wrapped_request_completes = WRAPPED_CYC_O && WRAPPED_ACK_I; + + reg [15:0] DAT_I_waiting; + reg DAT_I_received; + + assign RAW_ACK_I = WRAPPED_ACK_I && DAT_I_received; + assign RAW_ERR_I = 0; /* We'll start using it soon */ + assign RAW_DAT_I = {WRAPPED_DAT_I, DAT_I_waiting}; + assign RAW_STALL_I = !can_accept_request; + + always @ (posedge CLK_I) begin + if (WRAPPED_ACK_I) + DAT_I_waiting <= WRAPPED_DAT_I; + + if (RST_I) + DAT_I_received <= 0; + else if (wrapped_request_completes) + DAT_I_received <= !DAT_I_received; + end + +`ifdef SIMULATION + /* avoid undefined values */ + initial begin + request_out_waiting <= 0; + DAT_I_waiting <= 0; + end +`endif +endmodule // interface_wrapper diff --git a/tests/interface_wrapper/operations.memv b/tests/interface_wrapper/operations.memv new file mode 100644 index 0000000..2b581b5 --- /dev/null +++ b/tests/interface_wrapper/operations.memv @@ -0,0 +1,51 @@ +`include "macroasm.vh" // look into macroasm.vh for more info + +// First - a sequence of reads and writes like in self_32bit_word test +`WRITE(000000, deadbeef) +`WAIT +`READ (000000, deadbeef) +`WRITE(180004, 1234abcd) +`READ (000000, deadbeef) +`DESELECT +`DESELECT +`READ (180004, 1234abcd) +`WRITE(101010, a2a24444) +`WRITE(180004, 7c7c7c7c) +`READ (101010, a2a24444) +`WRITE(100004, 9901fe23) +`WAIT +`WAIT +`WAIT +`WAIT +`WAIT +`DESELECT +`DESELECT +`DESELECT +`WAIT +`READ(100004, 9901fe23) +`DESELECT +`WAIT +`READ(180004, 7c7c7c7c) + +// Now, a sequence with some word-aligned but not dword-aligned reads and writes +`WRITE(180006, bebebaba) +`READ (180004, baba7c7c) +`WAIT +`WRITE(18000a, 90907878) +`DESELECT +`WRITE(10100e, a1a1a0a0) +`READ (180008, 7878bebe) +`READ (101010, a2a2a1a1) +`WAIT +`DESELECT +`WAIT +`WRITE(004402, 2c0ffee5) +`READ (004402, 2c0ffee5) +`WRITE(004404, 00003c0f) +`WAIT +`WAIT +`WAIT +`READ (004402, 3c0ffee5) +`WRITE(012302, 0fca0000) +`WRITE(012306, 0000baca) +`READ (012304, baca0fca) diff --git a/tests/interface_wrapper/test.v b/tests/interface_wrapper/test.v new file mode 100644 index 0000000..cbd3d88 --- /dev/null +++ b/tests/interface_wrapper/test.v @@ -0,0 +1,160 @@ +/* adapted from self test */ +`default_nettype none + +`include "messages.vh" + +`ifndef MASTER_OPERATIONS_COUNT + `error_MASTER_OPERATIONS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + +`ifndef SIMULATION + `error_SIMULATION_not_defined +; /* Cause syntax error */ +`endif + +module interface_wrapper_test(); + wire M_CLK_I; + wire M_RST_I; + + wire M_RAW_ACK_I; + wire M_RAW_ERR_I; /* Not used yet, always low */ + wire [20:0] M_RAW_ADR_O; + wire [31:0] M_RAW_DAT_I; + wire [31:0] M_RAW_DAT_O; + wire [3:0] M_RAW_SEL_O; /* Not used yet, always 4'hF */ + wire M_RAW_STB_O; + wire M_RAW_CYC_O; + wire M_RAW_WE_O; + wire M_RAW_STALL_I; + + wire M_WRAPPED_ACK_I; + wire [19:0] M_WRAPPED_ADR_O; + wire [15:0] M_WRAPPED_DAT_I; + wire [15:0] M_WRAPPED_DAT_O; + wire M_WRAPPED_STB_O; + wire M_WRAPPED_CYC_O; + wire M_WRAPPED_WE_O; + wire M_WRAPPED_STALL_I; + + wire S_ACK_O; + wire S_CLK_I; + wire [19:0] S_ADR_I; + wire [15:0] S_DAT_I; + wire [15:0] S_DAT_O; + wire S_RST_I; + wire S_STB_I; + wire S_WE_I; + wire S_STALL_O; + + /* Non-wishbone */ + wire M_finished; + + master_model + #( + .MASTER_NR(0), + .WORD_SIZE(4), + .ADR_BITS(21), + .OPERATIONS_FILE("operations.mem"), + .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT) + ) master + ( + .ACK_I(M_RAW_ACK_I), + .CLK_I(M_CLK_I), + .ADR_O(M_RAW_ADR_O), + .DAT_I(M_RAW_DAT_I), + .DAT_O(M_RAW_DAT_O), + .RST_I(M_RST_I), + .STB_O(M_RAW_STB_O), + .CYC_O(M_RAW_CYC_O), + .WE_O(M_RAW_WE_O), + .STALL_I(M_RAW_STALL_I), + + .finished(M_finished) + ); + + memory_slave_model + #( + .SLAVE_NR(0), + .WORD_SIZE(2), + .ADR_BITS(20) + ) slave + ( + .ACK_O(S_ACK_O), + .CLK_I(S_CLK_I), + .ADR_I(S_ADR_I), + .DAT_I(S_DAT_I), + .DAT_O(S_DAT_O), + .RST_I(S_RST_I), + .STB_I(S_STB_I), + .WE_I(S_WE_I), + .STALL_O(S_STALL_O) + ); + +interface_wrapper wrapper + ( + .CLK_I(M_CLK_I), + .RST_I(M_RST_I), + + .RAW_ACK_I(M_RAW_ACK_I), + .RAW_ERR_I(M_RAW_ERR_I), + .RAW_ADR_O(M_RAW_ADR_O), + .RAW_DAT_I(M_RAW_DAT_I), + .RAW_DAT_O(M_RAW_DAT_O), + .RAW_SEL_O(M_RAW_SEL_O), + .RAW_STB_O(M_RAW_STB_O), + .RAW_CYC_O(M_RAW_CYC_O), + .RAW_WE_O(M_RAW_WE_O), + .RAW_STALL_I(M_RAW_STALL_I), + + .WRAPPED_ACK_I(M_WRAPPED_ACK_I), + .WRAPPED_ADR_O(M_WRAPPED_ADR_O), + .WRAPPED_DAT_I(M_WRAPPED_DAT_I), + .WRAPPED_DAT_O(M_WRAPPED_DAT_O), + .WRAPPED_STB_O(M_WRAPPED_STB_O), + .WRAPPED_CYC_O(M_WRAPPED_CYC_O), + .WRAPPED_WE_O(M_WRAPPED_WE_O), + .WRAPPED_STALL_I(M_WRAPPED_STALL_I) + ); + + reg CLK; + reg RST; + + assign M_CLK_I = CLK; + assign M_RST_I = RST; + + assign M_WRAPPED_ACK_I = S_ACK_O; + assign M_WRAPPED_DAT_I = S_DAT_O; + assign M_WRAPPED_STALL_I = S_STALL_O; + + assign M_RAW_SEL_O = 4'hF; + + assign S_CLK_I = CLK; + assign S_ADR_I = M_WRAPPED_ADR_O; + assign S_DAT_I = M_WRAPPED_DAT_O; + assign S_RST_I = RST; + assign S_STB_I = M_WRAPPED_STB_O && M_WRAPPED_CYC_O; + assign S_WE_I = M_WRAPPED_WE_O; + + integer i; + + initial begin + CLK <= 0; + RST <= 1; + + for (i = 0; i < 600; i++) begin + #1; + + CLK <= ~CLK; + + if (CLK) + RST <= 0; + + if (M_finished) + $finish; + end + + $display("error: master hasn't finished its operations in 300 ticks"); + $finish; + end +endmodule // interface_wrapper_test |