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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-02 14:20:39 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-02 14:20:39 +0200 |
| commit | 5cf95f5885033c04ce26c53a0e10e8f2636eac25 (patch) | |
| tree | c84c71f242e8260fc84efd46859dd5655601ff99 /tests/embedded_bram_slave/operations.memv | |
| parent | 8362f88d38e2baf0dc022e848c8d56b1a6476c5b (diff) | |
| download | AGH-engineering-thesis-5cf95f5885033c04ce26c53a0e10e8f2636eac25.tar.gz AGH-engineering-thesis-5cf95f5885033c04ce26c53a0e10e8f2636eac25.zip | |
add bench for embedded ram wishbone slave
Diffstat (limited to 'tests/embedded_bram_slave/operations.memv')
| -rw-r--r-- | tests/embedded_bram_slave/operations.memv | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/tests/embedded_bram_slave/operations.memv b/tests/embedded_bram_slave/operations.memv new file mode 100644 index 0000000..9cca800 --- /dev/null +++ b/tests/embedded_bram_slave/operations.memv @@ -0,0 +1,36 @@ +`include "macroasm.vh" // look into macroasm.vh for more info + +// First, check if memory initialization went ok +`READ (00000, 0000) // 0*7 at address 0 +`DESELECT +`READ (00001, 0007) // 1*7 at address 1 +`READ (00002, 000E) // 2*7 at address 2 +`WAIT +`WAIT +`READ (00089, 03BF) // 137*7 at address 137 +`READ (00101, 0707) // 257*7 at address 257 + +// Now, check that writing works (this is based on self test) +`WRITE(00000, abcd) +`WAIT +`READ (00000, abcd) +`WRITE(00001, 1234) +`READ (00000, abcd) +`DESELECT +`DESELECT +`READ (00001, 1234) +`WRITE(001E0, a2a2) +`WRITE(00001, 4321) +`READ (001E0, a2a2) +`WAIT +`WAIT +`WAIT +`WAIT +`WAIT +`DESELECT +`DESELECT +`DESELECT +`WAIT +`DESELECT +`WAIT +`READ(00001, 4321) |