start anew

2 files changed, 51 insertions, 0 deletions

diff --git a/include/macroasm.vh b/include/macroasm.vh
new file mode 100644
index 0000000..0c63ea7
--- /dev/null
+++ b/include/macroasm.vh
@@ -0,0 +1,33 @@
+`define C(comment) // make comments that disapper after preprocessing
+
+`C((
+This file implements a kind of macro assembly to generate instructions for our
+wishbone master mock module. The instructions specify what commands the master
+should send to its wishbone interface and what intervals it should put in
+between. $readmemh() is used to "load" the preprocessed instructions into
+the simulation.
+
+This header should be `included in the file with macroassembly operations.
+
+To generate the actual memory file you can for example use the -E flag to
+IVerilog, like this:
+$ iverilog -E some_operations.memv -o some_operations.mem
+
+I should have probably used some other tool for this job... POSIX shell, maybe?
+
+operations:
+  0 - read
+  1 - write
+  2 - wait (CYC_O high and STB_O low for one tick)
+  3 - deselect (CYC_O low for one tick)
+))
+
+`define READ(addr, expected_data) 0``addr``expected_data
+`define WRITE(addr, data)         1``addr``data
+`define WAIT                      2xxxxxxxxx
+`define DESELECT                  3xxxxxxxxx
+
+`C((
+We have to take care to use the correct number of digits for addresses and
+datas - the macros don't validate their arguments!
+))
diff --git a/include/messages.vh b/include/messages.vh
new file mode 100644
index 0000000..83ab6a4
--- /dev/null
+++ b/include/messages.vh
@@ -0,0 +1,18 @@
+`ifndef MESSAGES_VH
+ `define MESSAGES_VH 1
+
+ `define MSG(msg) \
+     if (1) begin \
+	$write("[%0t] ", $time); \
+        $display msg; \
+     end else
+
+ `ifdef DEBUG
+  `define DBG(msg) `MSG(msg)
+ `else
+  `define DBG(msg) if (1)  begin end else
+ `endif
+
+`endif
+
+// Use like this: DBG(("Wishbone master: a = %x, b = %x", a, b))