add miscellaneous module, which controls led2 and button2 and provides a timer; include a testbench for timer and led

1 files changed, 20 insertions, 11 deletions

diff --git a/design/soc.v b/design/soc.v
index b395404..4171f1d 100644
--- a/design/soc.v
+++ b/design/soc.v
@@ -6,7 +6,7 @@
  *   slave 2 - VGA text-mode controller
  *   slave 3 - SPI master controller
  *   slave 4 - UART controller (yet to be added)
- *   slave 5 - miscellaneous registers (yet to be added)
+ *   slave 5 - miscellaneous registers
  *
  * The memory map from stack machine's viewpoint is as follows:
  *   h000000 - h0001FF - embedded RAM
@@ -24,7 +24,7 @@
  *   h140208 - h1403FF - undefined (actually, repetitions of SPI regs)
  *   h140400 - h17FFFF - undefined (actually, repetitions of SPI memory & regs)
  *   h180000 - h1BFFFF - UART (not implemented yet)
- *   h1C0000 - h1FFFFF - miscellaneous peripherals (not implemented yet)
+ *   h1C0000 - h1FFFFF - miscellaneous peripherals
  */
 `default_nettype none
 
@@ -213,18 +213,28 @@ module soc
 	.ss_n(spi_ss_n)
 	);
 
-   /*
-    * Slaves 4 and 5 will be UART controller and miscellaneous registers,
-    * but for now - they're omitted
-    */
+   miscellaneous_slave slave5
+     (
+      .ACK_O(S5_ACK_O),
+      .CLK_I(CLK),
+      .ADR_I(S5_ADR_I[2:0]),
+      .DAT_I(S5_DAT_I),
+      .DAT_O(S5_DAT_O),
+      .RST_I(RST),
+      .STB_I(S5_STB_I),
+      .WE_I(S5_WE_I),
+      .STALL_O(S5_STALL_O),
+
+      /* Non-wishbone */
+      .button2(button2),
+      .led2(led2)
+      );
+
+   /* Slaves 4 will be UART controller but for now - it's omitted */
    assign S4_ACK_O = 1;
    assign S4_DAT_O = 0;
    assign S4_STALL_O = 0;
 
-   assign S5_ACK_O = 1;
-   assign S5_DAT_O = 0;
-   assign S5_STALL_O = 0;
-
    intercon intercon
      (
       .CLK(CLK),
@@ -312,7 +322,6 @@ module soc
    assign RST = reset;
 
    assign led1 = !M_finished;
-   assign led2 = !M_finished;
 
 `ifdef SIMULATION
    /* avoid undefined values */