ifndef PROJ_DIR
PROJ_DIR := ./
endif

include $(PROJ_DIR)/Makefile.config

IVFLAGS += -I$(PROJ_DIR)/include/

vpath %.v $(PROJ_DIR)/design/:$(PROJ_DIR)/models/:$(PROJ_DIR)/examples/:.
vpath %.vh $(PROJ_DIR)/include:.
vpath %.pcf $(PROJ_DIR):.

FILE_LINES = $(shell grep -E '^[[:space:]]*[^[:space:]/]' -c $(1))

design.json yosys.log : design.v
	$(YOSYS) -p 'read_verilog -defer $<' \
		-p 'synth_ice40 -top $(TOPMODULE) -json design.json' \
		> yosys.log 2>&1

design.asc pnr.log: $(PCF) design.json
	$(PNR) --hx8k --asc design.asc --pcf $< --json design.json \
		--package ct256 > pnr.log 2>&1

design.bin : design.asc $(FLASH_DATA)
	$(ICEPACK) $< $@
ifdef FLASH_DATA
	cat $(FLASH_DATA) >> $@
endif

prog : design.bin
	sudo iceprogduino $<

%.mem : $(PROJ_DIR)/tclasm.tcl %.s.tcl
	tclsh $^ > $@

%.mem : $(PROJ_DIR)/tools/wasm_compile %.wasm
	$^ > $@

%.wasm : %.wat
	$(WAT2WASM) $< -o $@

include $(PROJ_DIR)/tools/Makefile.tools

TOOLS_TARGETS = $(addprefix $(PROJ_DIR)/tools/,$(TOOLS))

$(TOOLS_TARGETS) : $(PROJ_DIR)/tools/% :
	$(MAKE) -C $(dir $@) $*

FIND_TCLASM_BASE_NAMES = \
	$(basename $(basename $(shell find $(1) -name "*.s.tcl")))

FIND_WAT_BASE_NAMES = \
	$(basename $(shell find $(1) -name "*.wat"))

FIND_MEMV_BASE_NAMES = \
	$(basename $(shell find $(1) -name "*.memv"))

FIND_GENERATED_MEM_BASE_NAMES = \
	$(call FIND_TCLASM_BASE_NAMES,$(1)) \
	$(call FIND_WAT_BASE_NAMES,$(1)) \
	$(call FIND_MEMV_BASE_NAMES,$(1))

FIND_GENERATED_MEM_FILES = \
	$(addsuffix .mem,$(call FIND_GENERATED_MEM_BASE_NAMES,$(1)))

FIND_GENERATED_WASM_FILES = \
	$(addsuffix .wasm,$(call FIND_WAT_BASE_NAMES,$(1)))

FIND_GENERATED_FILES = \
	$(call FIND_GENERATED_MEM_FILES,$(1)) \
	$(call FIND_GENERATED_WASM_FILES,$(1))

VGAdump.ppm : $(PROJ_DIR)/tools/VGAdump2ppm VGAdump.mem
	grep -v // < VGAdump.mem | $< > $@

.PHONY : prog