1
2
3
4
5
6
7
8
9
10
|
CPSR (Current Program Status Register) is a register, bits of which contain and/or determine various aspects of execution, i.e. condition flags, execution state (arm, thumb or jazelle), endianness state, execution mode <link to doc explaining modes> and interrupt mask. This register is readable and writeable with the use of mrs and msr instructions from any PL1 mode, thus it is possible to change things like mode or interrupt mask by writing to this register.
Additionally, there are other registers with the same or simillar bit fields as CPSR. Those PSRs (Program Status Registers) are:
· APSR (Application Program Status Register)
· SPSRs (Saved Program Status Registers)
APSR is can be considered the same as CPSR or a view of CPSR, with some limitations - some bit fields from CPSR are missing (reserved) in APSR. APSR can be accessed from PL0, while CPSR should only be accessed from PL1. This was an application program executing in user mode can learn some of the settings in CPSR without accessing CPSR directly.
SPSR is used for exception handling. Each exception-taking mode has it's own SPSR (they can be called SPSR_sup, SPSR_irq, etc.). On exception entry, old contents of CPSR are backed up in entered mode's SPSR. Instructions used for exception return (subs and ldm ^), when writing to the pc, have the important additional effect of copying the SPSR to CPSR. This way, on return from an exception, processor returns to the state from before the exception (this includes endianness settings, execution state, etc.).
In our project, the structure of PSRs is defined in terms of C bitfield structs in src/arm/PL1/kernel/psr.h.
|
