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Diffstat (limited to 'MMU-explained.txt')
| -rw-r--r-- | MMU-explained.txt | 37 |
1 files changed, 19 insertions, 18 deletions
diff --git a/MMU-explained.txt b/MMU-explained.txt index 91d3caa..a26c670 100644 --- a/MMU-explained.txt +++ b/MMU-explained.txt @@ -31,25 +31,26 @@ If MMU is present, general configuration of it is done through registers of the ### Coprocessor 15 Coprocessor 15 contains several registers, that control the behaviour of the MMU. They are all accessed through mcr and mrc arm instructions. -1. SCTLR, System Control Register - "provides the top level control of the system, including its memory system" - Bits of this register control, among other things: - · whether the MMU is enabled - · whether data cache is enabled - · whether instruction cache is enabled - · whether TEX remap is enabled - TEX remap is a feature, that changes how some translation table entry bit fields (called C, B and TEX) are used. We're not using TEX remap in our project. - · whether access flags are enabled - Enabling access flag causes one translation table descriptor bit normally used to specify access permissions of a region to be used as access flag. We don't use this feature either -2. DACR, Domain Access Control Register - "defines the access permission for each of the sixteen memory domains" - Entries in translation table define which of available 16 memory domains a memory region belongs to. Bits of DACR specify what permissions apply to each of the domains. Possible setting are to allow accesses to regions based on settings in translation table descriptor or to allow/disallow all accesses regardless of access permission bits in translation table. -3. TTBR0, Translation Table Base Register 0 - "holds the base address of translation table 0, and information about the memory it occupies" - System mode programmer can choose (with respect to some alignment requirements) where in the physical memory to put the translation table. Chosen address (actually, only a number of it's leftmost bits) has to be put in TTBR for the MMU to know where the table lies. Other bits of this register control some memory attributes relevant for accesses to table entries by the MMU +1. SCTLR, System Control Register - "provides the top level control of the system, including its memory system". Bits of this register control, among other things, whether the following are enabled: + + 1. the MMU + 2. data cache4. TEX remap + 3. instruction cache + 4. TEX remap (changes how some translation table entry bit fields (called C, B and TEX) are used - not in the project) + 5. access flags (enabling causes one translation table descriptor bit normally used to specify access permissions of a region to be used as access flag - not used either) + +2. DACR, Domain Access Control Register - "defines the access permission for each of the sixteen memory domains". Entries in translation table define which of available 16 memory domains a memory region belongs to. Bits of DACR specify what permissions apply to each of the domains. Possible settings are to allow accesses to regions based on settings in translation table descriptor or to allow/disallow all accesses regardless of access permission bits in translation table. + +3. TTBR0, Translation Table Base Register 0 - "holds the base address of translation table 0, and information about the memory it occupies". System mode programmer can choose (with respect to some alignment requirements) where in the physical memory to put the translation table. Chosen address (actually, only a number of it's leftmost bits) has to be put in TTBR for the MMU to know where the table lies. Other bits of this register control some memory attributes relevant for accesses to table entries by the MMU + 3. TTBR1, Translation Table Base Register 1 - simillar function to TTBR0 (see below for explaination of dual TTBR) -4. TTBCR, Translation Table Base Control Register - Bits of this register control - · How TLBs (Translation Lookaside Buffers) are used. TLBs are a mechanism of caching translation table entries. - · Whether to use some extension feature, that changes traslation table entries and TTBR* lengths to 64-bit (we're not using this, so we won't go into details) - · How a translation table is selected. There can be 2 translation tables and there are 2 cp15 registers (TTBR0 and TTBR1) to hold their base addresses. When 2 tables are in use, then on each memory access some leftmost bits of virtual address determine which one should be used. If the bits are all 0s - TTBR0-pointed table is used. Otherwise - TTBR1 is used. This allows OS developer to use separate translation tables for kernelspace and userspace (i.e. by having the kernelspace code run from virtual addresses starting with 1 and userspace code run from virtual addresses starting with 0). A field of TTBCR determines how many leftmost bits of virtual address are used for that (and also affects TTBR0 format). In the simplest setup (as in our project) this number is 0, so only the table specified in TTBR0 is used. +4. TTBCR, Translation Table Base Control Register, which controls: + + 1. How TLBs (Translation Lookaside Buffers) are used. TLBs are a mechanism of caching translation table entries. + 2. Whether to use some extension feature, that changes traslation table entries and TTBR* lengths to 64-bit (we're not using this, so we won't go into details) + 3. How a translation table is selected. + +There can be 2 translation tables and there are 2 cp15 registers (TTBR0 and TTBR1) to hold their base addresses. When 2 tables are in use, then on each memory access some leftmost bits of virtual address determine which one should be used. If the bits are all 0s - TTBR0-pointed table is used. Otherwise - TTBR1 is used. This allows OS developer to use separate translation tables for kernelspace and userspace (i.e. by having the kernelspace code run from virtual addresses starting with 1 and userspace code run from virtual addresses starting with 0). A field of TTBCR determines how many leftmost bits of virtual address are used for that (and also affects TTBR0 format). In the simplest setup (as in our project) this number is 0, so only the table specified in TTBR0 is used. ### Translation table |