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-rw-r--r--armclock.h22
-rw-r--r--bcmclock.h10
-rw-r--r--global.h12
-rw-r--r--uart.c52
-rw-r--r--uart.h22
5 files changed, 57 insertions, 61 deletions
diff --git a/armclock.h b/armclock.h
index f81f363..32d6517 100644
--- a/armclock.h
+++ b/armclock.h
@@ -41,38 +41,36 @@ static inline void armclk_init(void)
ctrl.fields.timer_enable = 1;
ctrl.fields.interrupt_enable = 1;
ctrl.fields.counter_23bit = 1;
- *(uint32_t volatile*) ARMCLK_CONTROL = ctrl.raw;
+ wr32(ARMCLK_CONTROL, ctrl.raw);
}
static inline void armclk_enable_timer_irq(void)
{
- armclk_control_t ctrl =
- (armclk_control_t) *(uint32_t volatile*) ARMCLK_CONTROL;
+ armclk_control_t ctrl = (armclk_control_t) rd32(ARMCLK_CONTROL);
ctrl.fields.interrupt_enable = 1;
- *(uint32_t volatile*) ARMCLK_CONTROL = ctrl.raw;
+ wr32(ARMCLK_CONTROL, ctrl.raw);
- *(uint32_t volatile*) ARM_ENABLE_BASIC_IRQS = 1;
+ wr32(ARM_ENABLE_BASIC_IRQS, 1);
}
static inline void armclk_disable_timer_irq(void)
{
- armclk_control_t ctrl =
- (armclk_control_t) *(uint32_t volatile*) ARMCLK_CONTROL;
+ armclk_control_t ctrl = (armclk_control_t) rd32(ARMCLK_CONTROL);
ctrl.fields.interrupt_enable = 0;
- *(uint32_t volatile*) ARMCLK_CONTROL = ctrl.raw;
+ wr32(ARMCLK_CONTROL, ctrl.raw);
- *(uint32_t volatile*) ARM_DISABLE_BASIC_IRQS = 1;
+ wr32(ARM_DISABLE_BASIC_IRQS, 1);
}
static inline void armclk_irq_settimeout(uint32_t timeout)
{
- *(uint32_t volatile*) ARMCLK_IRQ_CLR_ACK = 0;
- *(uint32_t volatile*) ARMCLK_LOAD = timeout;
+ wr32(ARMCLK_IRQ_CLR_ACK, 0);
+ wr32(ARMCLK_LOAD, timeout);
}
static inline _Bool armclk_irq_pending(void)
{
- return *(uint32_t volatile*) ARM_IRQ_BASIC_PENDING & 1;
+ return rd32(ARM_IRQ_BASIC_PENDING) & 1;
}
#endif // ARMCLOCK_H
diff --git a/bcmclock.h b/bcmclock.h
index dd7136b..7070283 100644
--- a/bcmclock.h
+++ b/bcmclock.h
@@ -17,19 +17,19 @@
static inline void bcmclk_enable_timer_irq(void)
{
- *(uint32_t volatile*) ARM_ENABLE_IRQS_1 = 1 << 3;
+ wr32(ARM_ENABLE_IRQS_1, 1 << 3);
}
static inline void bcmclk_disable_timer_irq(void)
{
- *(uint32_t volatile*) ARM_DISABLE_IRQS_1 = 1 << 3;
+ wr32(ARM_DISABLE_IRQS_1, 1 << 3);
}
static inline void bcmclk_irq_settimeout(uint32_t timeout)
{
- uint32_t clock_now = *(uint32_t volatile*) ST_CLO;
- *(uint32_t volatile*) ST_C3 = clock_now + timeout;
- *(uint32_t volatile*) ST_CS = 1 << 3;
+ uint32_t clock_now = rd32(ST_CLO);
+ wr32(ST_C3, clock_now + timeout);
+ wr32(ST_CS, 1 << 3);
}
#endif // BCMCLOCK_H
diff --git a/global.h b/global.h
index f5fe9a6..c461703 100644
--- a/global.h
+++ b/global.h
@@ -1,6 +1,8 @@
#ifndef GLOBAL_H
#define GLOBAL_H
+#include <stdint.h>
+
// board type, raspi2
#define RASPI 2
@@ -38,4 +40,14 @@
#define ARM_DISABLE_IRQS_2 (ARM_BASE + 0x220)
#define ARM_DISABLE_BASIC_IRQS (ARM_BASE + 0x224)
+inline static uint32_t rd32(uint32_t addr)
+{
+ return *(uint32_t volatile*) addr;
+}
+
+inline static void wr32(uint32_t addr, uint32_t value)
+{
+ *(uint32_t volatile*) addr = value;
+}
+
#endif // GLOBAL_H
diff --git a/uart.c b/uart.c
index c4ae445..2d4e176 100644
--- a/uart.c
+++ b/uart.c
@@ -3,18 +3,6 @@
#include <uart.h>
#include <global.h>
-// Memory-Mapped I/O output
-static inline void mmio_write(uint32_t reg, uint32_t data)
-{
- *(volatile uint32_t*)reg = data;
-}
-
-// Memory-Mapped I/O input
-static inline uint32_t mmio_read(uint32_t reg)
-{
- return *(volatile uint32_t*)reg;
-}
-
// Loop <delay> times in a way that the compiler won't optimize away
static inline void delay(int32_t count)
{
@@ -25,22 +13,20 @@ static inline void delay(int32_t count)
void uart_init()
{
// Disable PL011_UART.
- mmio_write(PL011_UART_CR, 0x00000000);
+ wr32(PL011_UART_CR, 0);
+
// Setup the GPIO pin 14 && 15.
// Disable pull up/down for all GPIO pins & delay for 150 cycles.
- mmio_write(GPPUD, 0x00000000);
+ wr32(GPPUD, 0);
delay(150);
// Disable pull up/down for pin 14,15 & delay for 150 cycles.
- mmio_write(GPPUDCLK0, (1 << 14) | (1 << 15));
+ wr32(GPPUDCLK0, (1 << 14) | (1 << 15));
delay(150);
// Write 0 to GPPUDCLK0 to make it take effect.
- mmio_write(GPPUDCLK0, 0x00000000);
-
- // Clear pending interrupts.
- mmio_write(PL011_UART_ICR, 0x7FF);
+ wr32(GPPUDCLK0, 0);
// Set integer & fractional part of baud rate.
// Divider = UART_CLOCK/(16 * Baud)
@@ -48,60 +34,60 @@ void uart_init()
// UART_CLOCK = 3000000; Baud = 115200.
// Divider = 3000000 / (16 * 115200) = 1.627 = ~1.
- mmio_write(PL011_UART_IBRD, 1);
+ wr32(PL011_UART_IBRD, 1);
// Fractional part register = (.627 * 64) + 0.5 = 40.6 = ~40.
- mmio_write(PL011_UART_FBRD, 40);
+ wr32(PL011_UART_FBRD, 40);
// Set 8 bit data transmission (1 stop bit, no parity)
// and disable FIFO to be able to receive interrupt every received
// char, not every 2 chars
- mmio_write(PL011_UART_LCRH, (1 << 5) | (1 << 6));
+ wr32(PL011_UART_LCRH, (1 << 5) | (1 << 6));
// set interrupt to come when transmit FIFO becomes ≤ 1/8 full
// or receive FIFO becomes ≥ 1/8 full
// (not really matters, since we disabled FIFOs)
- mmio_write(PL011_UART_IFLS, 0);
+ wr32(PL011_UART_IFLS, 0);
// Enable PL011_UART, receive & transfer part of UART.2
- mmio_write(PL011_UART_CR, (1 << 0) | (1 << 8) | (1 << 9));
+ wr32(PL011_UART_CR, (1 << 0) | (1 << 8) | (1 << 9));
// At first, it's probably safer to disable interrupts :)
uart_irq_disable();
- // That disables the entire uart irq; also disable single sources
- // within it
- *(uint32_t volatile*) PL011_UART_IMSC = 0;
+ // The above disables the entire uart irq;
+ // Also disable single sources within it
+ wr32(PL011_UART_IMSC, 0);
}
inline static _Bool can_transmit(void)
{
- return !(mmio_read(PL011_UART_FR) & (1 << 5));
+ return !(rd32(PL011_UART_FR) & (1 << 5));
}
inline static _Bool can_receive(void)
{
- return !(mmio_read(PL011_UART_FR) & (1 << 4));
+ return !(rd32(PL011_UART_FR) & (1 << 4));
}
void putchar(char c)
{
while (!can_transmit());
- mmio_write(PL011_UART_DR, c);
+ wr32(PL011_UART_DR, c);
}
char getchar(void)
{
while (!can_receive());
- return mmio_read(PL011_UART_DR);
+ return rd32(PL011_UART_DR);
}
_Bool putchar_non_blocking(char c)
{
if (can_transmit())
{
- mmio_write(PL011_UART_DR, c);
+ wr32(PL011_UART_DR, c);
return 0;
}
@@ -111,7 +97,7 @@ _Bool putchar_non_blocking(char c)
int getchar_non_blocking(void)
{
if (can_receive())
- return mmio_read(PL011_UART_DR);
+ return rd32(PL011_UART_DR);
return -1;
}
diff --git a/uart.h b/uart.h
index 892ba0e..72f7f94 100644
--- a/uart.h
+++ b/uart.h
@@ -47,59 +47,59 @@ int getchar_non_blocking(void);
static inline _Bool uart_irq_pending(void)
{
return
- ((uint32_t) 1 << 25) & *(uint32_t volatile*) ARM_IRQ_PENDING_2;
+ ((uint32_t) 1 << 25) & rd32(ARM_IRQ_PENDING_2);
}
static inline void uart_irq_disable(void)
{
// Mask uart in arm peripheral interrupts
- *(uint32_t volatile*) ARM_DISABLE_IRQS_2 = ((uint32_t) 1 << 25);
+ wr32(ARM_DISABLE_IRQS_2, ((uint32_t) 1) << 25);
}
static inline void uart_irq_enable(void)
{
// Unmask uart in arm peripheral interrupts
- *(uint32_t volatile*) ARM_ENABLE_IRQS_2 = ((uint32_t) 1 << 25);
+ wr32(ARM_ENABLE_IRQS_2, ((uint32_t) 1) << 25);
}
static inline _Bool uart_recv_irq_pending(void)
{
- return ((uint32_t) 1 << 4) & *(uint32_t volatile*) PL011_UART_MIS;
+ return (1 << 4) & rd32(PL011_UART_MIS);
}
static inline void uart_recv_irq_disable(void)
{
- *(uint32_t volatile*) PL011_UART_IMSC &= ~(1 << 4);
+ wr32(PL011_UART_IMSC, rd32(PL011_UART_IMSC) & ~(1 << 4));
}
static inline void uart_recv_irq_enable(void)
{
- *(uint32_t volatile*) PL011_UART_IMSC |= (1 << 4);
+ wr32(PL011_UART_IMSC, rd32(PL011_UART_IMSC) | (1 << 4));
}
static inline void uart_clear_recv_irq(void)
{
- *(uint32_t volatile*) PL011_UART_ICR = (1 << 4);
+ wr32(PL011_UART_ICR, (1 << 4));
}
static inline _Bool uart_send_irq_pending(void)
{
- return ((uint32_t) 1 << 5) & *(uint32_t volatile*) PL011_UART_MIS;
+ return (1 << 5) & rd32(PL011_UART_MIS);
}
static inline void uart_send_irq_disable(void)
{
- *(uint32_t volatile*) PL011_UART_IMSC &= ~(1 << 5);
+ wr32(PL011_UART_IMSC, rd32(PL011_UART_IMSC) & ~(1 << 5));
}
static inline void uart_send_irq_enable(void)
{
- *(uint32_t volatile*) PL011_UART_IMSC |= (1 << 5);
+ wr32(PL011_UART_IMSC, rd32(PL011_UART_IMSC) | (1 << 5));
}
static inline void uart_clear_send_irq(void)
{
- *(uint32_t volatile*) PL011_UART_ICR = (1 << 5);
+ wr32(PL011_UART_ICR, (1 << 5));
}
#endif // UART_H
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