fix interrupt enabling/disabling/polling and uart fifo setting to make the io work properly

1 files changed, 9 insertions, 2 deletions

diff --git a/uart.c b/uart.c
index c9fcd35..c4ae445 100644
--- a/uart.c
+++ b/uart.c
@@ -52,11 +52,14 @@ void uart_init()
   // Fractional part register = (.627 * 64) + 0.5 = 40.6 = ~40.
   mmio_write(PL011_UART_FBRD, 40);
 
-  // Enable FIFO & 8 bit data transmission (1 stop bit, no parity).
-  mmio_write(PL011_UART_LCRH, (1 << 4) | (1 << 5) | (1 << 6));
+  // Set 8 bit data transmission (1 stop bit, no parity)
+  // and disable FIFO to be able to receive interrupt every received
+  // char, not every 2 chars
+  mmio_write(PL011_UART_LCRH, (1 << 5) | (1 << 6));
 
   // set interrupt to come when transmit FIFO becomes ≤ 1/8 full
   // or receive FIFO becomes ≥ 1/8 full
+  // (not really matters, since we disabled FIFOs)
   mmio_write(PL011_UART_IFLS, 0);
 
   // Enable PL011_UART, receive & transfer part of UART.2
@@ -64,6 +67,10 @@ void uart_init()
 
   // At first, it's probably safer to disable interrupts :)
   uart_irq_disable();
+
+  // That disables the entire uart irq; also disable single sources
+  // within it
+  *(uint32_t volatile*) PL011_UART_IMSC = 0;
 }
 
 inline static _Bool can_transmit(void)