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author | vetch <vetch97@gmail.com> | 2020-01-17 20:49:32 +0100 |
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committer | vetch <vetch97@gmail.com> | 2020-01-17 20:49:32 +0100 |
commit | dfd6177fea6769a0e7dcd2d2205e5a795bba3553 (patch) | |
tree | e11cd7794da7f283f177e36bbb906b3111d51883 /src/arm/PL1/kernel/interrupts.c | |
parent | c0ce14c3fd8b598fceacdf0a194420f8acd924bf (diff) | |
parent | 9ed55d7612be0ffd17e3e9cc08bea7225470ee67 (diff) | |
download | rpi-MMU-example-dfd6177fea6769a0e7dcd2d2205e5a795bba3553.tar.gz rpi-MMU-example-dfd6177fea6769a0e7dcd2d2205e5a795bba3553.zip |
Merge branch 'bob' of https://repo.or.cz/RPi-MMU-example into alice
# Conflicts:
# src/arm/PL1/kernel/interrupts.c
Diffstat (limited to 'src/arm/PL1/kernel/interrupts.c')
-rw-r--r-- | src/arm/PL1/kernel/interrupts.c | 27 |
1 files changed, 1 insertions, 26 deletions
diff --git a/src/arm/PL1/kernel/interrupts.c b/src/arm/PL1/kernel/interrupts.c index 2c3c752..5695e6f 100644 --- a/src/arm/PL1/kernel/interrupts.c +++ b/src/arm/PL1/kernel/interrupts.c @@ -4,6 +4,7 @@ #include "armclock.h" #include "scheduler.h" +// defined in setup.c void __attribute__((noreturn)) setup(void); // from what I've heard, reset is never used on the Pi; @@ -101,29 +102,3 @@ void fiq_handler(void) { error("fiq happened"); } - - -/* Old, not sure if working interrupt function */ -//void -//__attribute__((interrupt("IRQ"))) -//__attribute__((section(".interrupt_vectors.text"))) -//irq_handler2(void) { -//// uart_puts("GOT INTERRUPT!\r\n"); -// -// local_timer_clr_reload_reg_t temp = { .IntClear = 1, .Reload = 1 }; -// QA7->TimerClearReload = temp; // Clear interrupt & reload -//} - -//int enable_timer(void) { -// -// QA7->TimerRouting.Routing = LOCALTIMER_TO_CORE0_IRQ; // Route local timer IRQ to Core0 -// QA7->TimerControlStatus.ReloadValue = 100; // Timer period set -// QA7->TimerControlStatus.TimerEnable = 1; // Timer enabled -// QA7->TimerControlStatus.IntEnable = 1; // Timer IRQ enabled -// QA7->TimerClearReload.IntClear = 1; // Clear interrupt -// QA7->TimerClearReload.Reload = 1; // Reload now -// QA7->Core0TimerIntControl.nCNTPNSIRQ_IRQ = 1; // We are in NS EL1 so enable IRQ to core0 that level -// QA7->Core0TimerIntControl.nCNTPNSIRQ_FIQ = 0; // Make sure FIQ is zero -//// uart_puts("Enabled Timer\r\n"); -// return(0); -//}
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