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authorvetch <vetch97@gmail.com>2020-01-13 12:40:38 +0100
committervetch <vetch97@gmail.com>2020-01-13 12:40:38 +0100
commit1af7591e37d09ddcd734ea07d0e999cf61c8bc5e (patch)
treea56c73c9eddeb148baffc3a31bf50edbbeb31074 /src/arm/PL1/kernel/bcmclock.h
parent300cf770698142b636da867b7e04bf2d6ae9baa4 (diff)
downloadrpi-MMU-example-1af7591e37d09ddcd734ea07d0e999cf61c8bc5e.tar.gz
rpi-MMU-example-1af7591e37d09ddcd734ea07d0e999cf61c8bc5e.zip
Great Reorganisation, modify structure and makefile
Diffstat (limited to 'src/arm/PL1/kernel/bcmclock.h')
-rw-r--r--src/arm/PL1/kernel/bcmclock.h35
1 files changed, 35 insertions, 0 deletions
diff --git a/src/arm/PL1/kernel/bcmclock.h b/src/arm/PL1/kernel/bcmclock.h
new file mode 100644
index 0000000..462346d
--- /dev/null
+++ b/src/arm/PL1/kernel/bcmclock.h
@@ -0,0 +1,35 @@
+#ifndef BCMCLOCK_H
+#define BCMCLOCK_H
+
+#include <stdint.h>
+#include "interrupts.h"
+#include "global.h"
+
+#define ST_BASE (PERIF_BASE + 0x3000) // System Timer
+
+#define ST_CS (ST_BASE + 0x0) // System Timer Control/Status
+#define ST_CLO (ST_BASE + 0x4) // System Timer Counter Lower 32 bits
+#define ST_CHI (ST_BASE + 0x8) // System Timer Counter Higher 32 bits
+#define ST_C0 (ST_BASE + 0xC) // System Timer Compare 0
+#define ST_C1 (ST_BASE + 0x10) // System Timer Compare 1
+#define ST_C2 (ST_BASE + 0x14) // System Timer Compare 2
+#define ST_C3 (ST_BASE + 0x18) // System Timer Compare 3
+
+static inline void bcmclk_enable_timer_irq(void)
+{
+ wr32(ARM_ENABLE_IRQS_1, 1 << 3);
+}
+
+static inline void bcmclk_disable_timer_irq(void)
+{
+ wr32(ARM_DISABLE_IRQS_1, 1 << 3);
+}
+
+static inline void bcmclk_irq_settimeout(uint32_t timeout)
+{
+ uint32_t clock_now = rd32(ST_CLO);
+ wr32(ST_C3, clock_now + timeout);
+ wr32(ST_CS, 1 << 3);
+}
+
+#endif // BCMCLOCK_H