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author | vetch <vetch97@gmail.com> | 2019-11-05 16:54:28 +0100 |
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committer | vetch <vetch97@gmail.com> | 2019-11-05 16:54:28 +0100 |
commit | 2beaa82a116a7e855327d3702999c371920fb410 (patch) | |
tree | 2b09111c608e64e8d846f0ad4455a1aac29a18a4 /kernel.c | |
parent | dcd4da0d9386e2f48a1161b3464116c2ba90234f (diff) | |
parent | d3da1d80ac2ce844b19feab6187722fc72eaa59c (diff) | |
download | rpi-MMU-example-2beaa82a116a7e855327d3702999c371920fb410.tar.gz rpi-MMU-example-2beaa82a116a7e855327d3702999c371920fb410.zip |
merge bob into alice
Diffstat (limited to 'kernel.c')
-rw-r--r-- | kernel.c | 52 |
1 files changed, 28 insertions, 24 deletions
@@ -1,4 +1,5 @@ -#include <uart.h> +#include "uart.h" +#include "cpsr.h" void kernel_main(uint32_t r0, uint32_t r1, uint32_t atags) { @@ -20,16 +21,16 @@ void kernel_main(uint32_t r0, uint32_t r1, uint32_t atags) // uart_puts("Hello, kernel World!\r\n"); char *paging; - - switch(ID_MMFR0 & 0xf) /* lowest 4 bits indicate VMSA support */ { - case 0 : paging = "no paging\n\r"; break; - case 1 : paging = "implementation defined paging\n\r\r\n"; break; - case 2 : paging = "VMSAv6, with cache and TLB type registers\n\r"; break; - case 3 : paging = "VMSAv7, with support for remapping and access flag\n\r"; break; - case 4 : paging = "VMSAv7 with PXN bit supported\n\r"; break; - case 5 : paging = "VMSAv7, PXN and long format descriptors. EPAE is supported.\n\r"; break; - default : paging = "?_? unknown paging ?_?\n\r"; - } + switch(ID_MMFR0 & 0xf) /* lowest 4 bits indicate VMSA support */ + { + case 0 : paging = "no paging\n\r"; break; + case 1 : paging = "implementation defined paging\n\r"; break; + case 2 : paging = "VMSAv6, with cache and TLB type registers\n\r"; break; + case 3 : paging = "VMSAv7, with support for remapping and access flag\n\r"; break; + case 4 : paging = "VMSAv7 with PXN bit supported\n\r"; break; + case 5 : paging = "VMSAv7, PXN and long format descriptors. EPAE is supported.\n\r"; break; + default : paging = "?_? unknown paging ?_?\n\r"; + } uart_puts(paging); @@ -39,19 +40,22 @@ void kernel_main(uint32_t r0, uint32_t r1, uint32_t atags) asm("mrs %0, cpsr" : "=r" (CPSR) :: "memory"); char *mode; - - switch(CPSR & 0x1f) /* lowest 5 bits indicate processor mode */ { - case 0x10 : mode = "User (PL0)\r\n"; break; - case 0x11 : mode = "FIQ (PL1)\r\n"; break; - case 0x12 : mode = "IRQ (PL1)\r\n"; break; - case 0x13 : mode = "Supervisor (PL1)\r\n"; break; - case 0x16 : mode = "Monitor (PL1)\r\n"; break; - case 0x17 : mode = "Abort (PL1)\r\n"; break; - case 0x1a : mode = "Hyp (PL2)\r\n"; break; - case 0x1b : mode = "Undefined (PL1)\r\n"; break; - case 0x1f : mode = "System (PL1)\r\n"; break; - default : mode = "Unknown mode\r\n"; break; - } + + switch(read_processor_mode()) + { + case 0x10 : mode = "User (PL0)\r\n"; break; + case 0x11 : mode = "FIQ (PL1)\r\n"; break; + case 0x12 : mode = "IRQ (PL1)\r\n"; break; + case 0x13 : mode = "Supervisor (PL1)\r\n"; break; + case 0x16 : mode = "Monitor (PL1)\r\n"; break; + case 0x17 : mode = "Abort (PL1)\r\n"; break; + case 0x1a : mode = "Hyp (PL2)\r\n"; break; + case 0x1b : mode = "Undefined (PL1)\r\n"; break; + case 0x1f : mode = "System (PL1)\r\n"; break; + default : mode = "Unknown mode\r\n"; break; + } + + set_system_mode(); uart_puts(mode); |