aboutsummaryrefslogtreecommitdiff
path: root/global.h
diff options
context:
space:
mode:
authorvetch <vetch97@gmail.com>2020-01-02 17:54:31 +0100
committervetch <vetch97@gmail.com>2020-01-02 17:54:31 +0100
commitab7b754bb32022336527c1a2d5d710b95a589d0e (patch)
tree19f508f06c72efcbdd2cfad46949ed6f1ae45a3c /global.h
parent5e1e6796109c892c4300c3da17c35e7874a40107 (diff)
parent6bf5a3b8c6e8a5d1cb3fb4880a5d9688ab094c62 (diff)
downloadrpi-MMU-example-ab7b754bb32022336527c1a2d5d710b95a589d0e.tar.gz
rpi-MMU-example-ab7b754bb32022336527c1a2d5d710b95a589d0e.zip
Merge branch 'bob' of https://repo.or.cz/RPi-MMU-example into alice
# Conflicts: # .gitignore # PL0_test.ld # demo_functionality.c # interrupt_vector.S # interrupts.c # kernel.c # memory.h
Diffstat (limited to 'global.h')
-rw-r--r--global.h40
1 files changed, 32 insertions, 8 deletions
diff --git a/global.h b/global.h
index b041a65..f5fe9a6 100644
--- a/global.h
+++ b/global.h
@@ -4,14 +4,38 @@
// board type, raspi2
#define RASPI 2
+// conditionally #define PERIF_BASE
#if RASPI == 4
-#define GPIO_BASE 0xFE200000
-#else
-#if RASPI == 3 || RASPI == 2
-#define GPIO_BASE 0x3F200000
-#else
-#define GPIO_BASE 0x20200000
-#endif // RASPI == 3 || RASPI == 2
-#endif // RASPI == 4
+
+#define PERIF_BASE 0xFE000000
+
+#elif RASPI == 3 || RASPI == 2
+
+#define PERIF_BASE 0x3F000000
+
+#else // if RASPI == 1
+
+#define PERIF_BASE 0x20000000
+
+#endif
+
+// GPIO_BASE is #define'd in terms of PERIF_BASE
+// (as in sane kernels - like linux, not like in wiki.osdev codes...)
+#define GPIO_BASE (PERIF_BASE + 0x200000)
+
+// ARM control block
+// called "base address for the ARM interrupt register" elsewhere
+#define ARM_BASE (PERIF_BASE + 0xB000)
+
+#define ARM_IRQ_BASIC_PENDING (ARM_BASE + 0x200)
+#define ARM_IRQ_PENDING_1 (ARM_BASE + 0x204)
+#define ARM_IRQ_PENDING_2 (ARM_BASE + 0x208)
+#define ARM_FIQ_CONTROL (ARM_BASE + 0x20C)
+#define ARM_ENABLE_IRQS_1 (ARM_BASE + 0x210)
+#define ARM_ENABLE_IRQS_2 (ARM_BASE + 0x214)
+#define ARM_ENABLE_BASIC_IRQS (ARM_BASE + 0x218)
+#define ARM_DISABLE_IRQS_1 (ARM_BASE + 0x21C)
+#define ARM_DISABLE_IRQS_2 (ARM_BASE + 0x220)
+#define ARM_DISABLE_BASIC_IRQS (ARM_BASE + 0x224)
#endif // GLOBAL_H