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| author | Wojtek Kosior <kwojtus@protonmail.com> | 2020-01-02 13:43:06 +0100 |
|---|---|---|
| committer | Wojtek Kosior <kwojtus@protonmail.com> | 2020-01-02 13:43:06 +0100 |
| commit | 7da46d099e1d1909bf5d09ecedfea21481a7a3b9 (patch) | |
| tree | 7d8fcb4b15274023d2e5234fda87f8805749f0ea /bcmclock.h | |
| parent | 1d7ff3bda9b6cbd15deadc1b440d9c02113beec6 (diff) | |
| download | rpi-MMU-example-7da46d099e1d1909bf5d09ecedfea21481a7a3b9.tar.gz rpi-MMU-example-7da46d099e1d1909bf5d09ecedfea21481a7a3b9.zip | |
move general irq register definitions to global.h
Diffstat (limited to 'bcmclock.h')
| -rw-r--r-- | bcmclock.h | 20 |
1 files changed, 4 insertions, 16 deletions
@@ -15,28 +15,16 @@ #define ST_C2 (ST_BASE + 0x14) // System Timer Compare 2 #define ST_C3 (ST_BASE + 0x18) // System Timer Compare 3 -#define BCMCLK_IRQ_BASIC_PENDING (ARM_BASE + 0x200) -#define BCMCLK_IRQ_PENDING_1 (ARM_BASE + 0x204) -#define BCMCLK_IRQ_PENDING_2 (ARM_BASE + 0x208) -#define BCMCLK_FIQ_CONTROL (ARM_BASE + 0x20C) -#define BCMCLK_ENABLE_IRQS_1 (ARM_BASE + 0x210) -#define BCMCLK_ENABLE_IRQS_2 (ARM_BASE + 0x214) -#define BCMCLK_ENABLE_BASIC_IRQS (ARM_BASE + 0x218) -#define BCMCLK_DISABLE_IRQS_1 (ARM_BASE + 0x21C) -#define BCMCLK_DISABLE_IRQS_2 (ARM_BASE + 0x220) -#define BCMCLK_DISABLE_BASIC_IRQS (ARM_BASE + 0x224) - - static inline void bcmclk_enable_timer_irq(void) { - *(uint32_t volatile*) BCMCLK_ENABLE_BASIC_IRQS = 1; - *(uint32_t volatile*) BCMCLK_ENABLE_IRQS_1 = 1 << 2; + *(uint32_t volatile*) ARM_ENABLE_BASIC_IRQS = 1; + *(uint32_t volatile*) ARM_ENABLE_IRQS_1 = 1 << 2; } static inline void bcmclk_disable_timer_irq(void) { - *(uint32_t volatile*) BCMCLK_DISABLE_BASIC_IRQS = 1; - *(uint32_t volatile*) BCMCLK_DISABLE_IRQS_1 = 1 << 2; + *(uint32_t volatile*) ARM_DISABLE_BASIC_IRQS = 1; + *(uint32_t volatile*) ARM_DISABLE_IRQS_1 = 1 << 2; } static inline void bcmclk_irq_settimeout(uint32_t timeout) |