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| author | Wojtek Kosior <kwojtus@protonmail.com> | 2020-01-15 16:47:14 +0100 |
|---|---|---|
| committer | Wojtek Kosior <kwojtus@protonmail.com> | 2020-01-15 16:47:14 +0100 |
| commit | ca3bf744f826225bb041afc4779ee19493d5440e (patch) | |
| tree | c6cf284059f9cf0bdcc48eea5d37988d9870e712 | |
| parent | 65328387c7880af777dcfd9c399cb453a87b44c1 (diff) | |
| download | rpi-MMU-example-ca3bf744f826225bb041afc4779ee19493d5440e.tar.gz rpi-MMU-example-ca3bf744f826225bb041afc4779ee19493d5440e.zip | |
remove garbage-comments
| -rw-r--r-- | src/arm/PL1/kernel/interrupts.c | 33 |
1 files changed, 1 insertions, 32 deletions
diff --git a/src/arm/PL1/kernel/interrupts.c b/src/arm/PL1/kernel/interrupts.c index 121d79c..5695e6f 100644 --- a/src/arm/PL1/kernel/interrupts.c +++ b/src/arm/PL1/kernel/interrupts.c @@ -3,11 +3,8 @@ #include "svc_interface.h" #include "armclock.h" #include "scheduler.h" -/** - @brief The undefined instruction interrupt handler -**/ - +// defined in setup.c void __attribute__((noreturn)) setup(void); // from what I've heard, reset is never used on the Pi; @@ -105,31 +102,3 @@ void fiq_handler(void) { error("fiq happened"); } - - -/* Here is your interrupt function */ -//void -//__attribute__((interrupt("IRQ"))) -//__attribute__((section(".interrupt_vectors.text"))) -//irq_handler2(void) { -// /* You code goes here */ -//// uart_puts("GOT INTERRUPT!\r\n"); -// -// local_timer_clr_reload_reg_t temp = { .IntClear = 1, .Reload = 1 }; -// QA7->TimerClearReload = temp; // Clear interrupt & reload -//} - -///* here is your main */ -//int enable_timer(void) { -// -// QA7->TimerRouting.Routing = LOCALTIMER_TO_CORE0_IRQ; // Route local timer IRQ to Core0 -// QA7->TimerControlStatus.ReloadValue = 100; // Timer period set -// QA7->TimerControlStatus.TimerEnable = 1; // Timer enabled -// QA7->TimerControlStatus.IntEnable = 1; // Timer IRQ enabled -// QA7->TimerClearReload.IntClear = 1; // Clear interrupt -// QA7->TimerClearReload.Reload = 1; // Reload now -// QA7->Core0TimerIntControl.nCNTPNSIRQ_IRQ = 1; // We are in NS EL1 so enable IRQ to core0 that level -// QA7->Core0TimerIntControl.nCNTPNSIRQ_FIQ = 0; // Make sure FIQ is zero -//// uart_puts("Enabled Timer\r\n"); -// return(0); -//}
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