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| author | Ludovic Courtès <ludo@gnu.org> | 2022-04-28 16:24:46 +0200 |
|---|---|---|
| committer | Ludovic Courtès <ludo@gnu.org> | 2022-04-28 16:24:46 +0200 |
| commit | 284fa7264963acc5d114ef5d54c347126b1654ba (patch) | |
| tree | 3e5360fcc81b6d0dce76a65aca60cf8528f2931f /gnu/packages/fpga.scm | |
| parent | 12c9da35389dfba86ae0d863132a6b2c4374205a (diff) | |
| parent | 882cacc1bb5be0df334dd7ce55b385a3a1678728 (diff) | |
| download | guix-284fa7264963acc5d114ef5d54c347126b1654ba.tar.gz guix-284fa7264963acc5d114ef5d54c347126b1654ba.zip | |
Merge branch 'master' into staging
Diffstat (limited to 'gnu/packages/fpga.scm')
| -rw-r--r-- | gnu/packages/fpga.scm | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index 3b2938aff0..b8f98ca63e 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -5,6 +5,7 @@ ;;; Copyright © 2019 Amin Bandali <bandali@gnu.org> ;;; Copyright © 2020 Vinicius Monego <monego@posteo.net> ;;; Copyright © 2021 Andrew Miloradovsky <andrew@interpretmath.pw> +;;; Copyright © 2022 Christian Gelinek <cgelinek@radlogic.com.au> ;;; ;;; This file is part of GNU Guix. ;;; @@ -111,7 +112,7 @@ formal verification.") (arguments `(#:make-flags (list (string-append "CC=" ,(cc-for-target))))) (native-inputs - (list flex bison ghostscript)) ; ps2pdf + (list flex bison ghostscript zlib)) ; ps2pdf (home-page "http://iverilog.icarus.com/") (synopsis "FPGA Verilog simulation and synthesis tool") (description "Icarus Verilog is a Verilog simulation and synthesis tool. |