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| author | Cayetano Santos <csantosb@inventati.org> | 2025-03-10 11:48:11 +0100 |
|---|---|---|
| committer | Ludovic Courtès <ludo@gnu.org> | 2025-03-21 13:39:44 +0100 |
| commit | 64e614d4ba7ce4a27c287d8f9c32d02ede5a3a2f (patch) | |
| tree | cd69f47c879fc6829196dea8fdd42473c3898788 | |
| parent | a9dcd548fb0cc807a6394bfb8efe89a679da64a0 (diff) | |
| download | guix-64e614d4ba7ce4a27c287d8f9c32d02ede5a3a2f.tar.gz guix-64e614d4ba7ce4a27c287d8f9c32d02ede5a3a2f.zip | |
gnu: Add python-vsg.
* gnu/packages/electronics.scm (python-vsg): New variable.
Change-Id: I373fa187e7af7ad79e5d885574ee124183d37f9b
Signed-off-by: Ludovic Courtès <ludo@gnu.org>
| -rw-r--r-- | gnu/packages/electronics.scm | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/gnu/packages/electronics.scm b/gnu/packages/electronics.scm index 93e37cf9ee..ce35b19432 100644 --- a/gnu/packages/electronics.scm +++ b/gnu/packages/electronics.scm @@ -31,6 +31,7 @@ #:use-module (guix utils) #:use-module (guix build-system gnu) #:use-module (guix build-system cmake) + #:use-module (guix build-system pyproject) #:use-module (gnu packages) #:use-module (gnu packages algebra) #:use-module (gnu packages autotools) @@ -53,6 +54,8 @@ #:use-module (gnu packages m4) #:use-module (gnu packages pkg-config) #:use-module (gnu packages python) + #:use-module (gnu packages python-build) + #:use-module (gnu packages python-check) #:use-module (gnu packages python-xyz) #:use-module (gnu packages serialization) #:use-module (gnu packages swig) @@ -566,3 +569,33 @@ Additionally your user must be member of the @code{plugdev} group.") "UHDM is a complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener.") (license license:asl2.0))) + +(define-public python-vsg + (package + (name "python-vsg") + (version "3.30.0") + (source + (origin + (method git-fetch) + (uri (git-reference + (url "https://github.com/jeremiah-c-leary/vhdl-style-guide/") + (commit version))) + (file-name (git-file-name name version)) + (sha256 + (base32 "0kgknd491s4ldmcw9s5j38frcfs55kxfifl52svy5q0vgg1qixq1")))) + (build-system pyproject-build-system) + (native-inputs (list python-setuptools + python-wheel + ;; tests + python-coverage + python-pytest + python-pytest-cov + python-pytest-html + python-pytest-xdist)) + (propagated-inputs (list python-pyyaml)) + (home-page "https://github.com/jeremiah-c-leary/vhdl-style-guide/") + (synopsis "Coding style enforcement for VHDL") + (description + "VSG lets you define a VHDL coding style and provides a command-line tool +to enforce it.") + (license license:gpl3+))) |