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Diffstat (limited to 'design/sram_slave.v')
| -rw-r--r-- | design/sram_slave.v | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/design/sram_slave.v b/design/sram_slave.v index 718ef8a..420626d 100644 --- a/design/sram_slave.v +++ b/design/sram_slave.v @@ -1,3 +1,38 @@ +/* + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | 262144x16-bit memory core (512 KB) | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | SLAVE, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 18-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE (determined by memory primitive, | + * | | about 100 MHz if using K6R4016V1D) | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | Special requirements | Circuit assumes the use of asynchronous | + * | | RAM primitive, e.g. K6R4016V1D. | + */ + `default_nettype none module sram_slave |