From ffb2c4adfb8e65e355b39abd39d994eebc649c98 Mon Sep 17 00:00:00 2001 From: Wojtek Kosior Date: Fri, 3 Jan 2020 04:53:01 +0100 Subject: add (not yet fully working - it can only send through uart now) interrupt-driven uart together with "scheduler" --- uart.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 49 insertions(+), 17 deletions(-) (limited to 'uart.c') diff --git a/uart.c b/uart.c index 2030538..c9fcd35 100644 --- a/uart.c +++ b/uart.c @@ -24,8 +24,8 @@ static inline void delay(int32_t count) void uart_init() { - // Disable UART0. - mmio_write(UART0_CR, 0x00000000); + // Disable PL011_UART. + mmio_write(PL011_UART_CR, 0x00000000); // Setup the GPIO pin 14 && 15. // Disable pull up/down for all GPIO pins & delay for 150 cycles. @@ -40,7 +40,7 @@ void uart_init() mmio_write(GPPUDCLK0, 0x00000000); // Clear pending interrupts. - mmio_write(UART0_ICR, 0x7FF); + mmio_write(PL011_UART_ICR, 0x7FF); // Set integer & fractional part of baud rate. // Divider = UART_CLOCK/(16 * Baud) @@ -48,31 +48,63 @@ void uart_init() // UART_CLOCK = 3000000; Baud = 115200. // Divider = 3000000 / (16 * 115200) = 1.627 = ~1. - mmio_write(UART0_IBRD, 1); + mmio_write(PL011_UART_IBRD, 1); // Fractional part register = (.627 * 64) + 0.5 = 40.6 = ~40. - mmio_write(UART0_FBRD, 40); + mmio_write(PL011_UART_FBRD, 40); // Enable FIFO & 8 bit data transmission (1 stop bit, no parity). - mmio_write(UART0_LCRH, (1 << 4) | (1 << 5) | (1 << 6)); + mmio_write(PL011_UART_LCRH, (1 << 4) | (1 << 5) | (1 << 6)); - // Mask all interrupts. - mmio_write(UART0_IMSC, (1 << 1) | (1 << 4) | (1 << 5) | (1 << 6) | - (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10)); + // set interrupt to come when transmit FIFO becomes ≤ 1/8 full + // or receive FIFO becomes ≥ 1/8 full + mmio_write(PL011_UART_IFLS, 0); - // Enable UART0, receive & transfer part of UART. - mmio_write(UART0_CR, (1 << 0) | (1 << 8) | (1 << 9)); + // Enable PL011_UART, receive & transfer part of UART.2 + mmio_write(PL011_UART_CR, (1 << 0) | (1 << 8) | (1 << 9)); + + // At first, it's probably safer to disable interrupts :) + uart_irq_disable(); +} + +inline static _Bool can_transmit(void) +{ + return !(mmio_read(PL011_UART_FR) & (1 << 5)); +} + +inline static _Bool can_receive(void) +{ + return !(mmio_read(PL011_UART_FR) & (1 << 4)); } void putchar(char c) { - // Wait for UART to become ready to transmit. - while ( mmio_read(UART0_FR) & (1 << 5) ) { } - mmio_write(UART0_DR, c); + while (!can_transmit()); + + mmio_write(PL011_UART_DR, c); } char getchar(void) { - // Wait for UART to have received something. - while ( mmio_read(UART0_FR) & (1 << 4) ) { } - return mmio_read(UART0_DR); + while (!can_receive()); + + return mmio_read(PL011_UART_DR); +} + +_Bool putchar_non_blocking(char c) +{ + if (can_transmit()) + { + mmio_write(PL011_UART_DR, c); + return 0; + } + + return 1; +} + +int getchar_non_blocking(void) +{ + if (can_receive()) + return mmio_read(PL011_UART_DR); + + return -1; } -- cgit v1.2.3 From 06991bb6572c1eb814ee35256b3c2bd06519acd2 Mon Sep 17 00:00:00 2001 From: Wojtek Kosior Date: Fri, 3 Jan 2020 16:41:41 +0100 Subject: fix interrupt enabling/disabling/polling and uart fifo setting to make the io work properly --- PL0_test.c | 2 -- armclock.h | 12 +++++++++++- interrupts.c | 11 +---------- scheduler.c | 4 +--- uart.c | 11 +++++++++-- uart.h | 4 ++-- 6 files changed, 24 insertions(+), 20 deletions(-) (limited to 'uart.c') diff --git a/PL0_test.c b/PL0_test.c index fed62a2..0bfebc7 100644 --- a/PL0_test.c +++ b/PL0_test.c @@ -8,8 +8,6 @@ void PL0_main(void) puts("Hello userspace! Type 'f' if you want me to try accessing " "kernel memory!"); - - asm volatile("mov r0, #17\n\rsvc #0" ::: "r0"); while (1) { char c = getchar(); diff --git a/armclock.h b/armclock.h index 2b2aec9..f81f363 100644 --- a/armclock.h +++ b/armclock.h @@ -46,11 +46,21 @@ static inline void armclk_init(void) static inline void armclk_enable_timer_irq(void) { + armclk_control_t ctrl = + (armclk_control_t) *(uint32_t volatile*) ARMCLK_CONTROL; + ctrl.fields.interrupt_enable = 1; + *(uint32_t volatile*) ARMCLK_CONTROL = ctrl.raw; + *(uint32_t volatile*) ARM_ENABLE_BASIC_IRQS = 1; } static inline void armclk_disable_timer_irq(void) { + armclk_control_t ctrl = + (armclk_control_t) *(uint32_t volatile*) ARMCLK_CONTROL; + ctrl.fields.interrupt_enable = 0; + *(uint32_t volatile*) ARMCLK_CONTROL = ctrl.raw; + *(uint32_t volatile*) ARM_DISABLE_BASIC_IRQS = 1; } @@ -62,7 +72,7 @@ static inline void armclk_irq_settimeout(uint32_t timeout) static inline _Bool armclk_irq_pending(void) { - return *(uint32_t volatile*) ARMCLK_RAW_IRQ; + return *(uint32_t volatile*) ARM_IRQ_BASIC_PENDING & 1; } #endif // ARMCLOCK_H diff --git a/interrupts.c b/interrupts.c index 9beee0a..bf7ed02 100644 --- a/interrupts.c +++ b/interrupts.c @@ -18,7 +18,7 @@ void undefined_instruction_vector(void) { error("Undefined instruction occured"); } -_Bool flag = 0; + uint32_t supervisor_call_handler(uint32_t regs[14]) { switch(regs[0]) { @@ -38,15 +38,6 @@ uint32_t supervisor_call_handler(uint32_t regs[14]) case UART_WRITE: error("UART_WRITE not implemented!!!!!"); break; - case 17: - { - flag = 1; - /* while (1) */ - /* { */ - /* printbin(*(uint32_t volatile*) PL011_UART_MIS); puts(""); */ - /* } */ - break; - } default: // perhaps we should kill the process now? error("unknown supervisor call type!!!!!"); diff --git a/scheduler.c b/scheduler.c index 3399bf4..141ba1d 100644 --- a/scheduler.c +++ b/scheduler.c @@ -113,7 +113,6 @@ schedule_save_context(uint32_t regs[14]) schedule(); } -extern _Bool flag; void __attribute__((noreturn)) schedule(void) { @@ -126,7 +125,6 @@ void __attribute__((noreturn)) schedule(void) new_CPSR.fields.PSR_IRQ_MASK_BIT = 0; write_CPSR(new_CPSR); - if (flag) putchar('l'); asm volatile("wfi"); @@ -146,8 +144,8 @@ void __attribute__((noreturn)) schedule(void) [stackaddr]"r" (PL0_sp), [linkaddr]"r" (PL0_lr) : "memory"); - armclk_enable_timer_irq(); armclk_irq_settimeout(0x00100000); + armclk_enable_timer_irq(); write_SPSR(PL0_PSR); diff --git a/uart.c b/uart.c index c9fcd35..c4ae445 100644 --- a/uart.c +++ b/uart.c @@ -52,11 +52,14 @@ void uart_init() // Fractional part register = (.627 * 64) + 0.5 = 40.6 = ~40. mmio_write(PL011_UART_FBRD, 40); - // Enable FIFO & 8 bit data transmission (1 stop bit, no parity). - mmio_write(PL011_UART_LCRH, (1 << 4) | (1 << 5) | (1 << 6)); + // Set 8 bit data transmission (1 stop bit, no parity) + // and disable FIFO to be able to receive interrupt every received + // char, not every 2 chars + mmio_write(PL011_UART_LCRH, (1 << 5) | (1 << 6)); // set interrupt to come when transmit FIFO becomes ≤ 1/8 full // or receive FIFO becomes ≥ 1/8 full + // (not really matters, since we disabled FIFOs) mmio_write(PL011_UART_IFLS, 0); // Enable PL011_UART, receive & transfer part of UART.2 @@ -64,6 +67,10 @@ void uart_init() // At first, it's probably safer to disable interrupts :) uart_irq_disable(); + + // That disables the entire uart irq; also disable single sources + // within it + *(uint32_t volatile*) PL011_UART_IMSC = 0; } inline static _Bool can_transmit(void) diff --git a/uart.h b/uart.h index ce27d4e..eba292a 100644 --- a/uart.h +++ b/uart.h @@ -61,7 +61,7 @@ static inline void uart_irq_enable(void) static inline _Bool uart_recv_irq_pending(void) { - return ((uint32_t) 1 << 4) & *(uint32_t volatile*) PL011_UART_RIS; + return ((uint32_t) 1 << 4) & *(uint32_t volatile*) PL011_UART_MIS; } static inline void uart_recv_irq_disable(void) @@ -81,7 +81,7 @@ static inline void uart_clear_recv_irq(void) static inline _Bool uart_send_irq_pending(void) { - return ((uint32_t) 1 << 5) & *(uint32_t volatile*) PL011_UART_RIS; + return ((uint32_t) 1 << 5) & *(uint32_t volatile*) PL011_UART_MIS; } static inline void uart_send_irq_disable(void) -- cgit v1.2.3 From 814d4a5357d849c4988422d48afa4aaa5432ce78 Mon Sep 17 00:00:00 2001 From: Wojtek Kosior Date: Fri, 3 Jan 2020 17:08:06 +0100 Subject: write to peripheral registers like humans --- armclock.h | 22 ++++++++++------------ bcmclock.h | 10 +++++----- global.h | 12 ++++++++++++ uart.c | 52 +++++++++++++++++++--------------------------------- uart.h | 22 +++++++++++----------- 5 files changed, 57 insertions(+), 61 deletions(-) (limited to 'uart.c') diff --git a/armclock.h b/armclock.h index f81f363..32d6517 100644 --- a/armclock.h +++ b/armclock.h @@ -41,38 +41,36 @@ static inline void armclk_init(void) ctrl.fields.timer_enable = 1; ctrl.fields.interrupt_enable = 1; ctrl.fields.counter_23bit = 1; - *(uint32_t volatile*) ARMCLK_CONTROL = ctrl.raw; + wr32(ARMCLK_CONTROL, ctrl.raw); } static inline void armclk_enable_timer_irq(void) { - armclk_control_t ctrl = - (armclk_control_t) *(uint32_t volatile*) ARMCLK_CONTROL; + armclk_control_t ctrl = (armclk_control_t) rd32(ARMCLK_CONTROL); ctrl.fields.interrupt_enable = 1; - *(uint32_t volatile*) ARMCLK_CONTROL = ctrl.raw; + wr32(ARMCLK_CONTROL, ctrl.raw); - *(uint32_t volatile*) ARM_ENABLE_BASIC_IRQS = 1; + wr32(ARM_ENABLE_BASIC_IRQS, 1); } static inline void armclk_disable_timer_irq(void) { - armclk_control_t ctrl = - (armclk_control_t) *(uint32_t volatile*) ARMCLK_CONTROL; + armclk_control_t ctrl = (armclk_control_t) rd32(ARMCLK_CONTROL); ctrl.fields.interrupt_enable = 0; - *(uint32_t volatile*) ARMCLK_CONTROL = ctrl.raw; + wr32(ARMCLK_CONTROL, ctrl.raw); - *(uint32_t volatile*) ARM_DISABLE_BASIC_IRQS = 1; + wr32(ARM_DISABLE_BASIC_IRQS, 1); } static inline void armclk_irq_settimeout(uint32_t timeout) { - *(uint32_t volatile*) ARMCLK_IRQ_CLR_ACK = 0; - *(uint32_t volatile*) ARMCLK_LOAD = timeout; + wr32(ARMCLK_IRQ_CLR_ACK, 0); + wr32(ARMCLK_LOAD, timeout); } static inline _Bool armclk_irq_pending(void) { - return *(uint32_t volatile*) ARM_IRQ_BASIC_PENDING & 1; + return rd32(ARM_IRQ_BASIC_PENDING) & 1; } #endif // ARMCLOCK_H diff --git a/bcmclock.h b/bcmclock.h index dd7136b..7070283 100644 --- a/bcmclock.h +++ b/bcmclock.h @@ -17,19 +17,19 @@ static inline void bcmclk_enable_timer_irq(void) { - *(uint32_t volatile*) ARM_ENABLE_IRQS_1 = 1 << 3; + wr32(ARM_ENABLE_IRQS_1, 1 << 3); } static inline void bcmclk_disable_timer_irq(void) { - *(uint32_t volatile*) ARM_DISABLE_IRQS_1 = 1 << 3; + wr32(ARM_DISABLE_IRQS_1, 1 << 3); } static inline void bcmclk_irq_settimeout(uint32_t timeout) { - uint32_t clock_now = *(uint32_t volatile*) ST_CLO; - *(uint32_t volatile*) ST_C3 = clock_now + timeout; - *(uint32_t volatile*) ST_CS = 1 << 3; + uint32_t clock_now = rd32(ST_CLO); + wr32(ST_C3, clock_now + timeout); + wr32(ST_CS, 1 << 3); } #endif // BCMCLOCK_H diff --git a/global.h b/global.h index f5fe9a6..c461703 100644 --- a/global.h +++ b/global.h @@ -1,6 +1,8 @@ #ifndef GLOBAL_H #define GLOBAL_H +#include + // board type, raspi2 #define RASPI 2 @@ -38,4 +40,14 @@ #define ARM_DISABLE_IRQS_2 (ARM_BASE + 0x220) #define ARM_DISABLE_BASIC_IRQS (ARM_BASE + 0x224) +inline static uint32_t rd32(uint32_t addr) +{ + return *(uint32_t volatile*) addr; +} + +inline static void wr32(uint32_t addr, uint32_t value) +{ + *(uint32_t volatile*) addr = value; +} + #endif // GLOBAL_H diff --git a/uart.c b/uart.c index c4ae445..2d4e176 100644 --- a/uart.c +++ b/uart.c @@ -3,18 +3,6 @@ #include #include -// Memory-Mapped I/O output -static inline void mmio_write(uint32_t reg, uint32_t data) -{ - *(volatile uint32_t*)reg = data; -} - -// Memory-Mapped I/O input -static inline uint32_t mmio_read(uint32_t reg) -{ - return *(volatile uint32_t*)reg; -} - // Loop times in a way that the compiler won't optimize away static inline void delay(int32_t count) { @@ -25,22 +13,20 @@ static inline void delay(int32_t count) void uart_init() { // Disable PL011_UART. - mmio_write(PL011_UART_CR, 0x00000000); + wr32(PL011_UART_CR, 0); + // Setup the GPIO pin 14 && 15. // Disable pull up/down for all GPIO pins & delay for 150 cycles. - mmio_write(GPPUD, 0x00000000); + wr32(GPPUD, 0); delay(150); // Disable pull up/down for pin 14,15 & delay for 150 cycles. - mmio_write(GPPUDCLK0, (1 << 14) | (1 << 15)); + wr32(GPPUDCLK0, (1 << 14) | (1 << 15)); delay(150); // Write 0 to GPPUDCLK0 to make it take effect. - mmio_write(GPPUDCLK0, 0x00000000); - - // Clear pending interrupts. - mmio_write(PL011_UART_ICR, 0x7FF); + wr32(GPPUDCLK0, 0); // Set integer & fractional part of baud rate. // Divider = UART_CLOCK/(16 * Baud) @@ -48,60 +34,60 @@ void uart_init() // UART_CLOCK = 3000000; Baud = 115200. // Divider = 3000000 / (16 * 115200) = 1.627 = ~1. - mmio_write(PL011_UART_IBRD, 1); + wr32(PL011_UART_IBRD, 1); // Fractional part register = (.627 * 64) + 0.5 = 40.6 = ~40. - mmio_write(PL011_UART_FBRD, 40); + wr32(PL011_UART_FBRD, 40); // Set 8 bit data transmission (1 stop bit, no parity) // and disable FIFO to be able to receive interrupt every received // char, not every 2 chars - mmio_write(PL011_UART_LCRH, (1 << 5) | (1 << 6)); + wr32(PL011_UART_LCRH, (1 << 5) | (1 << 6)); // set interrupt to come when transmit FIFO becomes ≤ 1/8 full // or receive FIFO becomes ≥ 1/8 full // (not really matters, since we disabled FIFOs) - mmio_write(PL011_UART_IFLS, 0); + wr32(PL011_UART_IFLS, 0); // Enable PL011_UART, receive & transfer part of UART.2 - mmio_write(PL011_UART_CR, (1 << 0) | (1 << 8) | (1 << 9)); + wr32(PL011_UART_CR, (1 << 0) | (1 << 8) | (1 << 9)); // At first, it's probably safer to disable interrupts :) uart_irq_disable(); - // That disables the entire uart irq; also disable single sources - // within it - *(uint32_t volatile*) PL011_UART_IMSC = 0; + // The above disables the entire uart irq; + // Also disable single sources within it + wr32(PL011_UART_IMSC, 0); } inline static _Bool can_transmit(void) { - return !(mmio_read(PL011_UART_FR) & (1 << 5)); + return !(rd32(PL011_UART_FR) & (1 << 5)); } inline static _Bool can_receive(void) { - return !(mmio_read(PL011_UART_FR) & (1 << 4)); + return !(rd32(PL011_UART_FR) & (1 << 4)); } void putchar(char c) { while (!can_transmit()); - mmio_write(PL011_UART_DR, c); + wr32(PL011_UART_DR, c); } char getchar(void) { while (!can_receive()); - return mmio_read(PL011_UART_DR); + return rd32(PL011_UART_DR); } _Bool putchar_non_blocking(char c) { if (can_transmit()) { - mmio_write(PL011_UART_DR, c); + wr32(PL011_UART_DR, c); return 0; } @@ -111,7 +97,7 @@ _Bool putchar_non_blocking(char c) int getchar_non_blocking(void) { if (can_receive()) - return mmio_read(PL011_UART_DR); + return rd32(PL011_UART_DR); return -1; } diff --git a/uart.h b/uart.h index 892ba0e..72f7f94 100644 --- a/uart.h +++ b/uart.h @@ -47,59 +47,59 @@ int getchar_non_blocking(void); static inline _Bool uart_irq_pending(void) { return - ((uint32_t) 1 << 25) & *(uint32_t volatile*) ARM_IRQ_PENDING_2; + ((uint32_t) 1 << 25) & rd32(ARM_IRQ_PENDING_2); } static inline void uart_irq_disable(void) { // Mask uart in arm peripheral interrupts - *(uint32_t volatile*) ARM_DISABLE_IRQS_2 = ((uint32_t) 1 << 25); + wr32(ARM_DISABLE_IRQS_2, ((uint32_t) 1) << 25); } static inline void uart_irq_enable(void) { // Unmask uart in arm peripheral interrupts - *(uint32_t volatile*) ARM_ENABLE_IRQS_2 = ((uint32_t) 1 << 25); + wr32(ARM_ENABLE_IRQS_2, ((uint32_t) 1) << 25); } static inline _Bool uart_recv_irq_pending(void) { - return ((uint32_t) 1 << 4) & *(uint32_t volatile*) PL011_UART_MIS; + return (1 << 4) & rd32(PL011_UART_MIS); } static inline void uart_recv_irq_disable(void) { - *(uint32_t volatile*) PL011_UART_IMSC &= ~(1 << 4); + wr32(PL011_UART_IMSC, rd32(PL011_UART_IMSC) & ~(1 << 4)); } static inline void uart_recv_irq_enable(void) { - *(uint32_t volatile*) PL011_UART_IMSC |= (1 << 4); + wr32(PL011_UART_IMSC, rd32(PL011_UART_IMSC) | (1 << 4)); } static inline void uart_clear_recv_irq(void) { - *(uint32_t volatile*) PL011_UART_ICR = (1 << 4); + wr32(PL011_UART_ICR, (1 << 4)); } static inline _Bool uart_send_irq_pending(void) { - return ((uint32_t) 1 << 5) & *(uint32_t volatile*) PL011_UART_MIS; + return (1 << 5) & rd32(PL011_UART_MIS); } static inline void uart_send_irq_disable(void) { - *(uint32_t volatile*) PL011_UART_IMSC &= ~(1 << 5); + wr32(PL011_UART_IMSC, rd32(PL011_UART_IMSC) & ~(1 << 5)); } static inline void uart_send_irq_enable(void) { - *(uint32_t volatile*) PL011_UART_IMSC |= (1 << 5); + wr32(PL011_UART_IMSC, rd32(PL011_UART_IMSC) | (1 << 5)); } static inline void uart_clear_send_irq(void) { - *(uint32_t volatile*) PL011_UART_ICR = (1 << 5); + wr32(PL011_UART_ICR, (1 << 5)); } #endif // UART_H -- cgit v1.2.3