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-rw-r--r--src/arm/PL1/kernel/interrupts.c27
-rw-r--r--src/arm/PL1/kernel/paging.c15
2 files changed, 13 insertions, 29 deletions
diff --git a/src/arm/PL1/kernel/interrupts.c b/src/arm/PL1/kernel/interrupts.c
index 2c3c752..5695e6f 100644
--- a/src/arm/PL1/kernel/interrupts.c
+++ b/src/arm/PL1/kernel/interrupts.c
@@ -4,6 +4,7 @@
#include "armclock.h"
#include "scheduler.h"
+// defined in setup.c
void __attribute__((noreturn)) setup(void);
// from what I've heard, reset is never used on the Pi;
@@ -101,29 +102,3 @@ void fiq_handler(void)
{
error("fiq happened");
}
-
-
-/* Old, not sure if working interrupt function */
-//void
-//__attribute__((interrupt("IRQ")))
-//__attribute__((section(".interrupt_vectors.text")))
-//irq_handler2(void) {
-//// uart_puts("GOT INTERRUPT!\r\n");
-//
-// local_timer_clr_reload_reg_t temp = { .IntClear = 1, .Reload = 1 };
-// QA7->TimerClearReload = temp; // Clear interrupt & reload
-//}
-
-//int enable_timer(void) {
-//
-// QA7->TimerRouting.Routing = LOCALTIMER_TO_CORE0_IRQ; // Route local timer IRQ to Core0
-// QA7->TimerControlStatus.ReloadValue = 100; // Timer period set
-// QA7->TimerControlStatus.TimerEnable = 1; // Timer enabled
-// QA7->TimerControlStatus.IntEnable = 1; // Timer IRQ enabled
-// QA7->TimerClearReload.IntClear = 1; // Clear interrupt
-// QA7->TimerClearReload.Reload = 1; // Reload now
-// QA7->Core0TimerIntControl.nCNTPNSIRQ_IRQ = 1; // We are in NS EL1 so enable IRQ to core0 that level
-// QA7->Core0TimerIntControl.nCNTPNSIRQ_FIQ = 0; // Make sure FIQ is zero
-//// uart_puts("Enabled Timer\r\n");
-// return(0);
-//} \ No newline at end of file
diff --git a/src/arm/PL1/kernel/paging.c b/src/arm/PL1/kernel/paging.c
index 771c681..6da9905 100644
--- a/src/arm/PL1/kernel/paging.c
+++ b/src/arm/PL1/kernel/paging.c
@@ -101,10 +101,11 @@ void setup_flat_map(void)
// enable MMU
puts("enabling the MMU");
- // redundant - we already have SCTLR contents in the variable
- // asm("mrc p15, 0, %0, c1, c0, 0" : "=r" (SCTLR.raw));
+ // we already have SCTLR contents in the variable
- SCTLR.fields.M = 1;
+ SCTLR.fields.M = 1; // enable MMU
+ SCTLR.fields.C = 1; // enable data cache
+ SCTLR.fields.I = 1; // enable instruction cache
asm("mcr p15, 0, %0, c1, c0, 0\n\r"
"isb" :: "r" (SCTLR.raw) : "memory");
@@ -241,6 +242,14 @@ uint16_t claim_and_map_section
// write modified descriptor to the table
*section_entry = descriptor;
+ // invalidate instruction cache
+ asm("mcr p15, 0, r0, c7, c5, 0\n\r" // r0 gets ignored
+ "isb" ::: "memory");
+
+ // invalidate branch-prediction
+ asm("mcr p15, 0, r0, c7, c5, 6\n\r" // r0 - same as above
+ "isb" ::: "memory");
+
// invalidate main Translation Lookup Buffer
asm("mcr p15, 0, r1, c8, c7, 0\n\r"
"isb" ::: "memory");