aboutsummaryrefslogtreecommitdiff
path: root/src/arm
diff options
context:
space:
mode:
authorWojtek Kosior <kwojtus@protonmail.com>2020-01-15 15:22:16 +0100
committerWojtek Kosior <kwojtus@protonmail.com>2020-01-15 15:22:16 +0100
commitc7b47accc6de3521f10c323983a1b325a60fb421 (patch)
treef1a4070e1a24568e11c97f368acc2e5b282289d5 /src/arm
parentf5c270d1b5177a9c0c006356ed2b8b32301d7491 (diff)
downloadrpi-MMU-example-c7b47accc6de3521f10c323983a1b325a60fb421.tar.gz
rpi-MMU-example-c7b47accc6de3521f10c323983a1b325a60fb421.zip
also enable data and instruction cache when enabling the MMU
Diffstat (limited to 'src/arm')
-rw-r--r--src/arm/PL1/kernel/paging.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arm/PL1/kernel/paging.c b/src/arm/PL1/kernel/paging.c
index 771c681..4c3dccf 100644
--- a/src/arm/PL1/kernel/paging.c
+++ b/src/arm/PL1/kernel/paging.c
@@ -101,10 +101,11 @@ void setup_flat_map(void)
// enable MMU
puts("enabling the MMU");
- // redundant - we already have SCTLR contents in the variable
- // asm("mrc p15, 0, %0, c1, c0, 0" : "=r" (SCTLR.raw));
+ // we already have SCTLR contents in the variable
- SCTLR.fields.M = 1;
+ SCTLR.fields.M = 1; // enable MMU
+ SCTLR.fields.C = 1; // enable data cache
+ SCTLR.fields.I = 1; // enable instruction cache
asm("mcr p15, 0, %0, c1, c0, 0\n\r"
"isb" :: "r" (SCTLR.raw) : "memory");